src/soc/amd/stoneyridge/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <amdblocks/acpi.h>
   5 #include <amdblocks/acpimmio.h>
   6 #include <amdblocks/psp.h>
   7 #include <amdblocks/smi.h>
   8 #include <amdblocks/smm.h>
   9 #include <arch/hlt.h>
  10 #include <arch/io.h>
  11 #include <console/console.h>
  12 #include <cpu/x86/cache.h>
  13 #include <cpu/x86/smm.h>
  14 #include <elog.h>
  15 #include <soc/smi.h>
  16 #include <soc/southbridge.h>
  17 #include <types.h>
  18
  19 /*
  20  * stoneyridge does not implement the APM_CNT_SMMINFO handler,
  21  * so it needs a special version
  22  */
  23 static void stoneyridge_fch_apmc_smi_handler(void)
  24 {
  25         const uint8_t cmd = apm_get_apmc();
  26
  27         switch (cmd) {
  28         case APM_CNT_ACPI_ENABLE:
  29                 acpi_clear_pm_gpe_status();
  30                 acpi_enable_sci();
  31                 break;
  32         case APM_CNT_ACPI_DISABLE:
  33                 acpi_disable_sci();
  34                 break;
  35         case APM_CNT_ELOG_GSMI:
  36                 if (CONFIG(ELOG_GSMI))
  37                         handle_smi_gsmi();
  38                 break;
  39         case APM_CNT_SMMSTORE:
  40                 if (CONFIG(SMMSTORE))
  41                         handle_smi_store();
  42                 break;
  43         }
  44
  45         mainboard_smi_apmc(cmd);
  46 }
  47
  48 static void fch_slp_typ_handler(void)
  49 {
  50         uint32_t pci_ctrl, reg32;
  51         uint16_t pm1cnt, reg16;
  52         uint8_t slp_typ, rst_ctrl;
  53
  54         /* Figure out SLP_TYP */
  55         pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
  56         printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt);
  57         slp_typ = acpi_sleep_from_pm1(pm1cnt);
  58
  59         /* Do any mainboard sleep handling */
  60         mainboard_smi_sleep(slp_typ);
  61
  62         switch (slp_typ) {
  63         case ACPI_S0:
  64                 printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
  65                 break;
  66         case ACPI_S3:
  67                 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
  68                 break;
  69         case ACPI_S4:
  70                 printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
  71                 break;
  72         case ACPI_S5:
  73                 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
  74                 break;
  75         default:
  76                 printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
  77                 break;
  78         }
  79
  80         if (slp_typ >= ACPI_S3) {
  81                 /* Sleep Type Elog S3, S4, and S5 entry */
  82                 elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
  83
  84                 wbinvd();
  85
  86                 clear_all_smi_status();
  87
  88                 /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
  89                 pci_ctrl = pm_read32(PM_PCI_CTRL);
  90                 pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
  91                 pci_ctrl |= FORCE_STPCLK_RETRY;
  92                 pm_write32(PM_PCI_CTRL, pci_ctrl);
  93
  94                 /* Enable SlpTyp */
  95                 rst_ctrl = pm_read8(PM_RST_CTRL1);
  96                 rst_ctrl |= SLPTYPE_CONTROL_EN;
  97                 pm_write8(PM_RST_CTRL1, rst_ctrl);
  98
  99                 /*
 100                  * Before the final command, check if there's pending wake
 101                  * event. Read enable first, so that reading the actual status
 102                  * is as close as possible to entering S3. The idea is to
 103                  * minimize the opportunity for a wake event to happen before
 104                  * actually entering S3. If there's a pending wake event, log
 105                  * it and continue normal path. S3 will fail and the wake event
 106                  * becomes a SCI.
 107                  */
 108                 if (CONFIG(ELOG_GSMI)) {
 109                         reg16 = acpi_read16(MMIO_ACPI_PM1_EN);
 110                         reg16 &= acpi_read16(MMIO_ACPI_PM1_STS);
 111                         if (reg16)
 112                                 elog_add_extended_event(
 113                                                 ELOG_SLEEP_PENDING_PM1_WAKE,
 114                                                 (u32)reg16);
 115
 116                         reg32 = acpi_read32(MMIO_ACPI_GPE0_EN);
 117                         reg32 &= acpi_read32(MMIO_ACPI_GPE0_STS);
 118                         if (reg32)
 119                                 elog_add_extended_event(
 120                                                 ELOG_SLEEP_PENDING_GPE0_WAKE,
 121                                                 reg32);
 122                 } /* if (CONFIG(ELOG_GSMI)) */
 123
 124                 /*
 125                  * An IO cycle is required to trigger the STPCLK/STPGNT
 126                  * handshake when the Pm1 write is reissued.
 127                  */
 128                 outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK));
 129                 hlt();
 130         }
 131 }
 132
 133 /*
 134  * Table of functions supported in the SMI handler.  Note that SMI source setup
 135  * in southbridge.c is unrelated to this list.
 136  */
 137 static const struct smi_sources_t smi_sources[] = {
 138         { .type = SMITYPE_SMI_CMD_PORT, .handler = stoneyridge_fch_apmc_smi_handler },
 139         { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler},
 140         { .type = SMITYPE_PSP, .handler = psp_smi_handler },
 141 };
 142
 143 void *get_smi_source_handler(int source)
 144 {
 145         size_t i;
 146
 147         for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++)
 148                 if (smi_sources[i].type == source)
 149                         return smi_sources[i].handler;
 150
 151         return NULL;
 152 }