src/southbridge/intel/i82801dx/i82801dx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef I82801DX_H
   4 #define I82801DX_H
   5
   6 #include <acpi/acpi.h>
   7 #include <device/device.h>
   8
   9 void i82801dx_enable(struct device *dev);
  10 void i82801dx_early_init(void);
  11 void i82801dx_lpc_setup(void);
  12
  13 #define DEBUG_PERIODIC_SMIS 0
  14
  15 #define MAINBOARD_POWER_OFF     0
  16 #define MAINBOARD_POWER_ON      1
  17 #define MAINBOARD_POWER_KEEP    2
  18
  19 /*
  20  * 000 = Non-combined. P0 is primary master. P1 is secondary master.
  21  * 001 = Non-combined. P0 is secondary master. P1 is primary master.
  22  * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
  23  *       Primary IDE channel disabled.
  24  * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
  25  * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
  26  *       slave; Secondary IDE channel disabled.
  27  * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
  28  */
  29 /* PCI Configuration Space (D31:F1) */
  30 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
  31 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
  32
  33 /* IDE_TIM bits */
  34 #define IDE_DECODE_ENABLE       (1 << 15)
  35
  36 #define PCI_DMA_CFG     0x90
  37 #define SERIRQ_CNTL     0x64
  38 #define GEN_CNTL        0xd0
  39 #define GEN_STS         0xd4
  40 #define RTC_CONF        0xd8
  41 #define GEN_PMCON_3     0xa4
  42
  43 #define PCICMD          0x04
  44 #define PMBASE          0x40
  45 #define   DEFAULT_PMBASE 0x0400
  46 #define ACPI_CNTL       0x44
  47 #define   ACPI_EN       (1 << 4)
  48 #define BIOS_CNTL       0x4E
  49 #define GPIO_BASE       0x58
  50 #define GPIO_CNTL       0x5C
  51 #define   GPIOBASE_ADDR 0x0500
  52 #define PIRQA_ROUT      0x60
  53 #define PIRQB_ROUT      0x61
  54 #define PIRQC_ROUT      0x62
  55 #define PIRQD_ROUT      0x63
  56 #define PIRQE_ROUT      0x68
  57 #define PIRQF_ROUT      0x69
  58 #define PIRQG_ROUT      0x6A
  59 #define PIRQH_ROUT      0x6B
  60 #define COM_DEC         0xE0
  61 #define GEN1_DEC        0xE4
  62 #define LPC_EN          0xE6
  63 #define FUNC_DIS        0xF2
  64
  65 /* 1e f0 244e */
  66
  67 #define CMD             0x04
  68 #define SBUS_NUM        0x19
  69 #define SUB_BUS_NUM     0x1A
  70 #define SMLT            0x1B
  71 #define IOBASE          0x1C
  72 #define IOLIM           0x1D
  73 #define MEMBASE         0x20
  74 #define MEMLIM          0x22
  75 #define CNF             0x50
  76 #define MTT             0x70
  77 #define PCI_MAST_STS    0x82
  78
  79 #define RTC_FAILED      (1 << 2)
  80
  81 #define PM1_STS         0x00
  82 #define   WAK_STS       (1 << 15)
  83 #define   PCIEXPWAK_STS (1 << 14)
  84 #define   PRBTNOR_STS   (1 << 11)
  85 #define   RTC_STS       (1 << 10)
  86 #define   PWRBTN_STS    (1 << 8)
  87 #define   GBL_STS       (1 << 5)
  88 #define   BM_STS        (1 << 4)
  89 #define   TMROF_STS     (1 << 0)
  90 #define PM1_EN          0x02
  91 #define   PCIEXPWAK_DIS (1 << 14)
  92 #define   RTC_EN        (1 << 10)
  93 #define   PWRBTN_EN     (1 << 8)
  94 #define   GBL_EN        (1 << 5)
  95 #define   TMROF_EN      (1 << 0)
  96 #define PM1_CNT         0x04
  97 #define   GBL_RLS       (1 << 2)
  98 #define   BM_RLD        (1 << 1)
  99 #define   SCI_EN        (1 << 0)
 100 #define PM1_TMR         0x08
 101 #define PROC_CNT        0x10
 102 #define LV2             0x14
 103 #define GPE0_STS        0x28
 104 #define   PME_B0_STS    (1 << 13)
 105 #define   USB3_STS      (1 << 12)
 106 #define   PME_STS       (1 << 11)
 107 #define   BATLOW_STS    (1 << 10)
 108 #define   GST_STS       (1 << 9)
 109 #define   RI_STS        (1 << 8)
 110 #define   SMB_WAK_STS   (1 << 7)
 111 #define   TCOSCI_STS    (1 << 6)
 112 #define   AC97_STS      (1 << 5)
 113 #define   USB2_STS      (1 << 4)
 114 #define   USB1_STS      (1 << 3)
 115 #define   SWGPE_STS     (1 << 2)
 116 #define   HOT_PLUG_STS  (1 << 1)
 117 #define   THRM_STS      (1 << 0)
 118 #define GPE0_EN         0x2c
 119 #define   PME_B0_EN     (1 << 13)
 120 #define   PME_EN        (1 << 11)
 121 #define SMI_EN          0x30
 122 #define   EL_SMI_EN      (1 << 25) // Intel Quick Resume Technology
 123 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 124 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 125 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 126 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 127 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 128 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 129 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 130 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 131 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 132 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 133 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 134 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 135 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 136 #define SMI_STS         0x34
 137 #define ALT_GP_SMI_EN   0x38
 138 #define ALT_GP_SMI_STS  0x3a
 139 #define GPE_CNTL        0x42
 140 #define DEVACT_STS      0x44
 141 #define SS_CNT          0x50
 142
 143 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 144 /* TCO1 Control Register */
 145 #define TCO1_CNT        0x68
 146 #endif
 147
 148 #define GEN_PMCON_1             0xa0
 149 #define GEN_PMCON_2             0xa2
 150 #define GEN_PMCON_3             0xa4
 151
 152 /* GEN_PMCON_3 bits */
 153 #define RTC_BATTERY_DEAD        (1 << 2)
 154 #define RTC_POWER_FAILED        (1 << 1)
 155 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
 156
 157 #endif /* I82801DX_H */