2 ========================================================================
4 The 4.20 release was done on May 15, 2023. Unfortunately, a licensing
5 issues was found immediately after the release was completed, and it
6 was decided to hold the release until that was fixed.
8 Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
9 4.20_branch will contain all code for 4.20, 4.20.1, and any further
10 changes required for this release.
12 The coreboot community has done a tremendous amount of work on the
13 codebase over the last three and a half months. We've had over 1600
14 commits in that time period, doing ongoing cleanup and improvement.
16 It can be hard to remember at times how much the codebase really has
17 improved, but looking back at coreboot code from previous years, it's
18 really impressive the changes that have happened. We'd like to thank
19 everyone who has been involved in these changes. It's great to work
20 with everyone involved, from the people who make the small cleanup
21 patches and review all of the incoming changes to the people working
22 on new chipsets and SoCs. We'd additionally like to thank all of those
23 individuals who make the effort to become involved and report issues
24 or push even a single patch to fix a bug that they've noticed.
26 Many thanks to everyone involved!
28 We plan to get the 4.21 release done in mid August, 2023.
31 Significant or interesting changes
32 ----------------------------------
35 ### cpu/mp_init.c: Only enable CPUs once they execute code
37 On some systems the BSP cannot know how many CPUs are present in the
38 system. A typical use case is a multi socket system. Setting the enable
39 flag only on CPUs that actually exist makes it more flexible.
42 ### cpu/x86/smm: Add PCI resource store functionality
44 In certain cases data within protected memory areas like SMRAM could
45 be leaked or modified if an attacker remaps PCI BARs to point within
46 that area. Add support to the existing SMM runtime to allow storing
47 PCI resources in SMRAM and then later retrieving them.
49 This helps prevent moving BARs around to get SMM to access memory in
50 areas that shouldn't be accessed.
53 ### acpi: Add SRAT x2APIC table support
55 For platforms using X2APIC mode add SRAT x2APIC table
56 generation. This allows the setup of proper SRAT tables.
59 ### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
61 This patch supports projects to use _DSM to control USB3 U1/U2
64 More details can be found in
65 https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
67 The ACPI and USB driver of linux kernel need corresponding functions
68 to support this feature. Please see
69 https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
72 ### drivers/efi: Add EFI variable store option support
74 Add a driver to read and write EFI variables stored in a region device.
75 This is particularly useful for EDK2 as payload and allows it to reuse
76 existing EFI tools to set/get options used by the firmware.
78 The write implementation is fault tolerant and doesn't corrupt the
79 variable store. A faulting write might result in using the old value
80 even though a 'newer' had been completely written.
82 Implemented basic unit tests for header corruption, writing existing
83 data and append new data into the store.
85 Initial firmware region state:
86 Initially the variable store region isn't formatted. Usually this is
87 done in the EDK2 payload when no valid firmware volume could be found.
88 It might be useful to do this offline or in coreboot to have a working
89 option store on the first boot or when it was corrupted.
91 Performance improvements:
92 Right now the code always checks if the firmware volume header is valid.
93 This could be optimised by caching the test result in heap. For write
94 operations it would be good to cache the end of the variable store in
95 the heap as well, instead of walking the whole store. For read
96 operations caching the entire store could be considered.
99 The EFI variable store is append write only. To update an existing
100 variable, first a new is written to the end of the store and then the
101 previous is marked invalid. This only works on PNOR flash that allow to
102 clear set bits, but keep cleared bits state.
103 This mechanisms allows a fault tolerant write, but it also requires to
104 "clean" the variable store from time to time. This cleaning would remove
105 variables that have been marked "deleted".
106 Such cleaning mechanism in turn must be fault tolerant and thus must use
107 a second partition in the SPI flash as backup/working region.
108 For now, cleaning is done in coreboot.
111 The driver should check if a previous write was successful and if not
112 mark variables as deleted on the next operation.
115 ### drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
117 Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
118 and prints EWL type 3 primarily associated with MRC training failures.
121 ### Toolchain updates
123 * Upgrade MPC from version 1.2.1 to 1.3.1
124 * Upgrade MPFR from version 4.1.1 to 4.2.0
125 * Upgrade CMake from version 3.25.0 to 3.26.3
126 * Upgrade LLVM from version 15.0.6 to 15.0.7
127 * Upgrade GCC from version 11.2.0 to 11.3.0
128 * Upgrade binutils from version 2.37 to 2.40
131 Additional coreboot changes
132 ---------------------------
134 * Remove Yabits payload. Yabits is deprecated and archived.
135 * Add DDR2 support to Intel GM45 code.
136 * Fix superiotool compilation issues when using musl-libc.
137 * Drop the Python 2 package from the coreboot-sdk.
138 * Drop the Zephyr SDK from coreboot-sdk since the packaged version
139 was quite old and wasn’t really used.
140 * Add inteltool support for the Intel "Emmitsburg" PCH.
141 * Work to improve cache hit percentage when rebuilding using ccache.
142 * Adding Sound-Open-Firmware drivers to chromebooks to enable audio on
143 non-chrome operating systems.
144 * Improve and expand ACPI generation code.
145 * Fix some issues for the RISC-V code.
146 * Continue upstreaming the POWER9 architecture.
147 * Add documentation for SBOM (Software Bill of Materials).
148 * Add SimNow console logging support for AMD.
149 * Do initial work on Xeon SPR
150 * CMOS defaults greater than 128 bytes long now extend to bank 1.
157 * Dell: Latitude E6400
160 * Google: Constitution
169 * HP: EliteBook 2170p
170 * Intel: Archer City CRB
173 * Protectli: VP4630/VP4650
185 * Intel Icelake U DDR4/LPDDR4 RVP
186 * Intel Icelake Y LPDDR4 RVP
193 * Removed soc/intel/icelake
196 Plans to move platform support to a branch
197 ------------------------------------------
199 ### Intel Quark SoC & Galileo mainboard
201 The SoC Intel Quark is unmaintained and different efforts to revive it
202 have so far failed. The only user of this SoC ever was the Galileo
205 Thus, to reduce the maintenance overhead for the community, support for
206 the following components will be removed from the master branch and will
207 be maintained on the release 4.20 branch.
210 * Intel Galileo mainboard
213 Statistics from the 4.19 to the 4.20 release
214 --------------------------------------------
217 Average Commits per day: 13.72
218 Total lines added: 102592
219 Average lines added per commit: 62.94
220 Number of patches adding more than 100 lines: 128
221 Average lines added per small commit: 37.99
222 Total lines removed: 34824
223 Average lines removed per commit: 21.36
224 Total difference between added and removed: 67768
229 Significant Known and Open Issues
230 ---------------------------------
232 Issues from the coreboot bugtracker: https://ticket.coreboot.org/
234 +-----+-----------------------------------------------------------------+
236 +=====+=================================================================+
237 | 478 | X200 booting Linux takes a long time with TSC |
238 +-----+-----------------------------------------------------------------+
239 | 474 | X200s crashes after graphic init with 8GB RAM |
240 +-----+-----------------------------------------------------------------+
241 | 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb |
242 +-----+-----------------------------------------------------------------+
243 | 453 | Intel HDMI / DP Audio device not showing up after libgfxinit |
244 +-----+-----------------------------------------------------------------+
245 | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
246 +-----+-----------------------------------------------------------------+
247 | 448 | Thinkpad T440P ACPI Battery Value Issues |
248 +-----+-----------------------------------------------------------------+
249 | 446 | Optiplex 9010 No Post |
250 +-----+-----------------------------------------------------------------+
251 | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
252 +-----+-----------------------------------------------------------------+
253 | 427 | x200: Two battery charging issues |
254 +-----+-----------------------------------------------------------------+
255 | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
256 +-----+-----------------------------------------------------------------+
257 | 412 | x230 reboots on suspend |
258 +-----+-----------------------------------------------------------------+
259 | 393 | T500 restarts rather than waking up from suspend |
260 +-----+-----------------------------------------------------------------+
261 | 350 | I225 PCIe device not detected on Harcuvar |
262 +-----+-----------------------------------------------------------------+
263 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
264 +-----+-----------------------------------------------------------------+