1 coreboot 4.7 release notes
2 ==========================
4 The 4.7 release covers commit 0a4a4f7ae4 to commit fd470f7163
5 Since the last release in April 2017, the coreboot project had 2573 commits by 150 authors.
7 There is a pgp signed 4.7 tag in the git repository, and a branch will be created as needed.
14 * Intel i82801jx Southbridge (ICH10)
15 * Intel Denverton and Denverton-NS
16 * Work has started on Intel Cannon Lake
18 Added 47 mainboards & variants:
21 * Acer Chromebook 14 CB3-431 [google/edgar] Intel Braswell
22 * Acer Chromebook 15 CB3-532 [google/banon] Intel Braswell
23 * Acer Chromebook N7 C731 [google/relm] Intel Braswell
24 * ASRock B75 Pro3-M Intel Ivy Bridge
25 * ASRock G41C-GS R2.0 Intel G41/ICH7
26 * Asus AM1I-A AMD Kabini
27 * Asus Chromebook C202SA/C300SA/C301SA (google/terra) Intel Braswell
28 * Biostar A68N-5200 AMD Kabini
29 * Compulab Intense-PC Intel Ivy Bridge
30 * Dell Chromebook 11 3180/3189 (google/kefka) Intel Braswell
31 * Foxconn G41S-K Intel G41/ICH7
32 * Google Coral Intel Apollo Lake
33 * Google Grunt AMD Stoney Ridge
34 * Google Kahlee AMD Stoney Ridge
35 * Google Meowth Intel Cannon Lake
36 * Google Nami Intel Kaby Lake
37 * Google Nautilus Intel Kaby Lake
38 * Google Nefario Rockchip RK3399
39 * Google Rainier Rockchip RK3399
40 * Google Soraka Intel Kaby Lake
41 * Google Zoombini Intel Cannon Lake
42 * HP Chromebook 11 G5 (google/setzer) Intel Braswell
43 * HP EliteBook 2570p Intel Ivy Bridge
44 * HP EliteBook 2760p Intel Sandy Bridge
45 * HP EliteBook 8460p Intel Sandy Bridge
46 * HP EliteBook 8470p Intel Ivy Bridge
47 * HP EliteBook Revolve 810 G1 Intel Ivy Bridge
48 * Intel Cannnlake RVPU Intel Cannon Lake
49 * Intel Cannonlake RVPY Intel Cannon Lake
50 * Intel D410PT Intel Atom D410
51 * Intel DG43GT Intel G43/ICH10
52 * Intel GLKRVP Intel Gemini Lake
53 * Intel Harcuvar Intel Denverton
54 * Intel NUC DCP847SKE Intel Sandy Bridge
55 * Intel Saddle Brook reference board Intel Skylake
56 * Lenovo N22/N42 Chromebook (google/reks) Intel Braswell
57 * Lenovo T430 Intel Ivy Bridge
58 * Lenovo Thinkpad 11e/Yoga Chromebook G3
59 (google/ultima) Intel Braswell
60 * Lenovo ThinkPad X131e Intel Sandy Bridge
61 * Lenovo Z61T Intel i945/ICH7
62 * PC Engines APU3 AMD Steppe Eagle
63 * PC Engines APU4 AMD Steppe Eagle
64 * PC Engines APU5 AMD Steppe Eagle
65 * Purism Librem 13 v2 Intel Skylake
66 * Purism Librem 15 v3 Intel Skylake
67 * Samsung Chromebook 3 (google/celes) Intel Braswell
68 * White label Chromebook (google/wizpig) Intel Braswell
69 * WinNET G170 VIA CN700
77 New Embedded Controller
78 -----------------------
80 * KBC1126 used in HP EliteBooks
85 * Integrate me_cleaner
86 * Add flashconsole implementation
87 * Build edk2 UEFI payload from upstream source
88 * Remove CMOS NVRAM configurable baud rates
89 * A common mrc_cache driver to store romstage settings in SPI flash
91 Google ChromeOS devices:
92 ------------------------
94 * Add ACPI USB port definitions for many boards
95 * Fix preprocessor guards for LPC TPM
96 * Remove non-existent IRQ for LPC TPM
97 * Fix LED control for mccloud
98 * Enable keyboard backlight at boot on equipped boards
99 * Fix ACPI data for non-google EC's to improve Windows compatibility
100 * Add missing SPD files for chell, fixing support for > 4GB boards
105 * Add support for passive cooling
106 * Add ACPI fan control
107 * Add BDC detection and power saving
108 * Unify hybrid graphics and improved power saving
113 * Add support for all outstanding Braswell ChromeOS devices
114 * Update FSP 1.1 header to v1.1.7.0
115 * Adjust FSP header revision check to be less stringent
116 * Upstream numerous commits from Chromium tree
117 * Fix ACPI scope for I2C devices
118 * Fix SPI write after flash lockdown set
123 * Unify Intel VBT handling
124 * Add support for loading external VBT
125 * Provide the VBT through Intel OpRegion method on all platforms
126 * Fix low memory corruption on S3 resume path
131 * Add a Kconfig option to ignore XMP max DIMMs
132 * Add Kconfig option for max. DRAM frequency fuses
133 * Advertise correct DRAM frequency on Ivy Bridge
134 * Improve CAS/frequency selection
135 * Use command rate 2T on channels with two DIMMs installed for improved
141 * Fix booting with FSB800 DDR667 combination
142 * Rework ram DQS receiver enable training sequence
143 * Rework and fix SPD reading and decoding
144 * Allow external GPU to take VGA cycles
149 * Improve compatibility with mixed DIMMs
150 * Add romstage timings
151 * Set the display backlight PWM correctly
156 * Enable remapping of memory to allow for 4G or more memory
161 * Implement early CBMEM support
162 * Fix RAM init programming
167 * Move boards to early CBMEM and add timestamps
168 * Refactor boards away from using agesawrapper
169 * Wipe unused sources under vendorcode
170 * Re-enable ACPI S3 after fixing low memory corruptions
175 * Move boards to early CBMEM
176 * Continue work on cleaning up headers
181 * Support new hardware: Broxton/APL (DP and HDMI only), Skylake
182 * Handle framebuffer mapping in the library
183 * Make DP training more compatible and tolerant
184 * Enhance compatibility for VGA adaptors
189 * Add support for Sunrise Point LP
190 * Add Intel Boot Guard detection
195 * buildgcc now verifies downloaded files against hashes
196 * Improve GNAT detection
197 * Update binutils to 2.29.1