payloads/libpayload/drivers/usb/uhci.c

   1 /*
   2  *
   3  * Copyright (C) 2008-2010 coresystems GmbH
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. The name of the author may not be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 //#define USB_DEBUG
  30
  31 #include <arch/virtual.h>
  32 #include <inttypes.h>
  33 #include <usb/usb.h>
  34 #include "uhci.h"
  35 #include "uhci_private.h"
  36
  37 static void uhci_start(hci_t *controller);
  38 static void uhci_stop(hci_t *controller);
  39 static void uhci_reset(hci_t *controller);
  40 static void uhci_shutdown(hci_t *controller);
  41 static int uhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
  42 static int uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
  43                          int dalen, u8 *data);
  44 static void* uhci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
  45 static void uhci_destroy_intr_queue(endpoint_t *ep, void *queue);
  46 static u8* uhci_poll_intr_queue(void *queue);
  47
  48 #if 0
  49 /* dump uhci */
  50 static void
  51 uhci_dump(hci_t *controller)
  52 {
  53         usb_debug("dump:\nUSBCMD: %x\n", uhci_reg_read16(controller, USBCMD));
  54         usb_debug("USBSTS: %x\n", uhci_reg_read16(controller, USBSTS));
  55         usb_debug("USBINTR: %x\n", uhci_reg_read16(controller, USBINTR));
  56         usb_debug("FRNUM: %x\n", uhci_reg_read16(controller, FRNUM));
  57         usb_debug("FLBASEADD: %x\n", uhci_reg_read32(controller, FLBASEADD));
  58         usb_debug("SOFMOD: %x\n", uhci_reg_read8(controller, SOFMOD));
  59         usb_debug("PORTSC1: %x\n", uhci_reg_read16(controller, PORTSC1));
  60         usb_debug("PORTSC2: %x\n", uhci_reg_read16(controller, PORTSC2));
  61 }
  62 #endif
  63
  64 static void td_dump(td_t *td)
  65 {
  66         usb_debug("+---------------------------------------------------+\n");
  67         if ((td->token & TD_PID_MASK) == UHCI_SETUP)
  68                 usb_debug("|..[SETUP]..........................................|\n");
  69         else if ((td->token & TD_PID_MASK) == UHCI_IN)
  70                 usb_debug("|..[IN].............................................|\n");
  71         else if ((td->token & TD_PID_MASK) == UHCI_OUT)
  72                 usb_debug("|..[OUT]............................................|\n");
  73         else
  74                 usb_debug("|..[]...............................................|\n");
  75         usb_debug("|:|============ UHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(td));
  76         usb_debug("|:+-----------------------------------------------+:|\n");
  77         usb_debug("|:| Next  TD/QH     [0x%08lx]                  |:|\n", td->ptr & ~0xFUL);
  78         usb_debug("|:+-----------------------------------------------+:|\n");
  79         usb_debug("|:| Depth/Breath [%lx]  | QH/TD [%lx] | TERMINATE [%lx] |:|\n",
  80         (td->ptr & (1UL << 2)) >> 2, (td->ptr & (1UL << 1)) >> 1, td->ptr & 1UL);
  81         usb_debug("|:+-----------------------------------------------+:|\n");
  82         usb_debug("|:|   T   | Maximum Length               | [%04lx] |:|\n", (td->token & (0x7FFUL << 21)) >> 21);
  83         usb_debug("|:|   O   | PID CODE                     | [%04"PRIx32"] |:|\n", td->token & 0xFF);
  84         usb_debug("|:|   K   | Endpoint                     | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT);
  85         usb_debug("|:|   E   | Device Address               | [%04lx] |:|\n", (td->token & (0x7FUL << 8)) >> 8);
  86         usb_debug("|:|   N   | Data Toggle                  |    [%lx] |:|\n", (td->token & (1UL << 19)) >> 19);
  87         usb_debug("|:+-----------------------------------------------+:|\n");
  88         usb_debug("|:|   C   | Short Packet Detector        |    [%lx] |:|\n", (td->ctrlsts & (1UL << 29)) >> 29);
  89         usb_debug("|:|   O   | Error Counter                |    [%lx] |:|\n",
  90                   (td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT);
  91         usb_debug("|:|   N   | Low Speed Device             |    [%lx] |:|\n", (td->ctrlsts & (1UL << 26)) >> 26);
  92         usb_debug("|:|   T   | Isochronous Select           |    [%lx] |:|\n", (td->ctrlsts & (1UL << 25)) >> 25);
  93         usb_debug("|:|   R   | Interrupt on Complete (IOC)  |    [%lx] |:|\n", (td->ctrlsts & (1UL << 24)) >> 24);
  94         usb_debug("|:+   O   ----------------------------------------+:|\n");
  95         usb_debug("|:|   L   | Active                       |    [%lx] |:|\n", (td->ctrlsts & (1UL << 23)) >> 23);
  96         usb_debug("|:|   &   | Stalled                      |    [%lx] |:|\n", (td->ctrlsts & (1UL << 22)) >> 22);
  97         usb_debug("|:|   S   | Data Buffer Error            |    [%lx] |:|\n", (td->ctrlsts & (1UL << 21)) >> 21);
  98         usb_debug("|:|   T   | Bubble Detected              |    [%lx] |:|\n", (td->ctrlsts & (1UL << 20)) >> 20);
  99         usb_debug("|:|   A   | NAK Received                 |    [%lx] |:|\n", (td->ctrlsts & (1UL << 19)) >> 19);
 100         usb_debug("|:|   T   | CRC/Timeout Error            |    [%lx] |:|\n", (td->ctrlsts & (1UL << 18)) >> 18);
 101         usb_debug("|:|   U   | Bitstuff Error               |    [%lx] |:|\n", (td->ctrlsts & (1UL << 17)) >> 17);
 102         usb_debug("|:|   S   ----------------------------------------|:|\n");
 103         usb_debug("|:|       | Actual Length                | [%04lx] |:|\n", td->ctrlsts & 0x7FFUL);
 104         usb_debug("|:+-----------------------------------------------+:|\n");
 105         usb_debug("|:| Buffer pointer  [0x%08"PRIx32"]                  |:|\n", td->bufptr);
 106         usb_debug("|:|-----------------------------------------------|:|\n");
 107         usb_debug("|...................................................|\n");
 108         usb_debug("+---------------------------------------------------+\n");
 109 }
 110
 111 static void
 112 uhci_reset(hci_t *controller)
 113 {
 114         /* reset */
 115         uhci_reg_write16(controller, USBCMD, 4); /* Global Reset */
 116         mdelay(50); /* uhci spec 2.1.1: at least 10ms */
 117         uhci_reg_write16(controller, USBCMD, 0);
 118         mdelay(10);
 119         uhci_reg_write16(controller, USBCMD, 2); /* Host Controller Reset */
 120         /* wait for controller to finish reset */
 121         /* TOTEST: how long to wait? 100ms for now */
 122         int timeout = 200; /* time out after 200 * 500us == 100ms */
 123         while (((uhci_reg_read16(controller, USBCMD) & 2) != 0) && timeout--)
 124                 udelay(500);
 125         if (timeout < 0)
 126                 usb_debug("Warning: uhci: host controller reset timed out.\n");
 127 }
 128
 129 static void
 130 uhci_reinit(hci_t *controller)
 131 {
 132         uhci_reg_write32(controller, FLBASEADD,
 133                           (u32) virt_to_phys(UHCI_INST(controller)->
 134                                               framelistptr));
 135         //usb_debug ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
 136
 137         /* disable irqs */
 138         uhci_reg_write16(controller, USBINTR, 0);
 139
 140         /* reset framelist index */
 141         uhci_reg_write16(controller, FRNUM, 0);
 142
 143         uhci_reg_write16(controller, USBCMD,
 144                          uhci_reg_read16(controller, USBCMD) | 0xc0);   // max packets, configure flag
 145
 146         uhci_start(controller);
 147 }
 148
 149 hci_t *
 150 uhci_pci_init(pcidev_t addr)
 151 {
 152         int i;
 153         u16 reg16;
 154
 155         hci_t *controller = new_controller();
 156         controller->pcidev = addr;
 157         controller->instance = xzalloc(sizeof(uhci_t));
 158         controller->type = UHCI;
 159         controller->start = uhci_start;
 160         controller->stop = uhci_stop;
 161         controller->reset = uhci_reset;
 162         controller->init = uhci_reinit;
 163         controller->shutdown = uhci_shutdown;
 164         controller->bulk = uhci_bulk;
 165         controller->control = uhci_control;
 166         controller->set_address = generic_set_address;
 167         controller->finish_device_config = NULL;
 168         controller->destroy_device = NULL;
 169         controller->create_intr_queue = uhci_create_intr_queue;
 170         controller->destroy_intr_queue = uhci_destroy_intr_queue;
 171         controller->poll_intr_queue = uhci_poll_intr_queue;
 172         init_device_entry(controller, 0);
 173         UHCI_INST(controller)->roothub = controller->devices[0];
 174
 175         /* ~1 clears the register type indicator that is set to 1
 176          * for IO space */
 177         controller->reg_base = pci_read_config32(addr, 0x20) & ~1;
 178
 179         /* kill legacy support handler */
 180         uhci_stop(controller);
 181         mdelay(1);
 182         uhci_reg_write16(controller, USBSTS, 0x3f);
 183         reg16 = pci_read_config16(addr, 0xc0);
 184         reg16 &= 0xdf80;
 185         pci_write_config16(addr, 0xc0, reg16);
 186
 187         UHCI_INST(controller)->framelistptr = memalign(0x1000, 1024 * sizeof(flistp_t));        /* 4kb aligned to 4kb */
 188         if (!UHCI_INST (controller)->framelistptr)
 189                 fatal("Not enough memory for USB frame list pointer.\n");
 190
 191         memset(UHCI_INST(controller)->framelistptr, 0,
 192                 1024 * sizeof(flistp_t));
 193
 194         /* According to the *BSD UHCI code, this one is needed on some
 195            PIIX chips, because otherwise they misbehave. It must be
 196            added to the last chain.
 197
 198            FIXME: this leaks, if the driver should ever be reinited
 199                   for some reason. Not a problem now.
 200            */
 201         td_t *antiberserk = memalign(16, sizeof(td_t));
 202         if (!antiberserk)
 203                 fatal("Not enough memory for chipset workaround.\n");
 204         memset(antiberserk, 0, sizeof(td_t));
 205
 206         UHCI_INST(controller)->qh_prei = memalign(16, sizeof(qh_t));
 207         UHCI_INST(controller)->qh_intr = memalign(16, sizeof(qh_t));
 208         UHCI_INST(controller)->qh_data = memalign(16, sizeof(qh_t));
 209         UHCI_INST(controller)->qh_last = memalign(16, sizeof(qh_t));
 210
 211         if (!UHCI_INST (controller)->qh_prei ||
 212             !UHCI_INST (controller)->qh_intr ||
 213             !UHCI_INST (controller)->qh_data ||
 214             !UHCI_INST (controller)->qh_last)
 215                 fatal("Not enough memory for USB controller queues.\n");
 216
 217         UHCI_INST(controller)->qh_prei->headlinkptr =
 218                 virt_to_phys(UHCI_INST(controller)->qh_intr) | FLISTP_QH;
 219         UHCI_INST(controller)->qh_prei->elementlinkptr = 0 | FLISTP_TERMINATE;
 220
 221         UHCI_INST(controller)->qh_intr->headlinkptr =
 222                 virt_to_phys(UHCI_INST(controller)->qh_data) | FLISTP_QH;
 223         UHCI_INST(controller)->qh_intr->elementlinkptr = 0 | FLISTP_TERMINATE;
 224
 225         UHCI_INST(controller)->qh_data->headlinkptr =
 226                 virt_to_phys(UHCI_INST(controller)->qh_last) | FLISTP_QH;
 227         UHCI_INST(controller)->qh_data->elementlinkptr = 0 | FLISTP_TERMINATE;
 228
 229         UHCI_INST(controller)->qh_last->headlinkptr = virt_to_phys(UHCI_INST(controller)->qh_data) | FLISTP_TERMINATE;
 230         UHCI_INST(controller)->qh_last->elementlinkptr = virt_to_phys(antiberserk) | FLISTP_TERMINATE;
 231
 232         for (i = 0; i < 1024; i++) {
 233                 UHCI_INST(controller)->framelistptr[i] =
 234                         virt_to_phys(UHCI_INST(controller)->qh_prei) | FLISTP_QH;
 235         }
 236         controller->devices[0]->controller = controller;
 237         controller->devices[0]->init = uhci_rh_init;
 238         controller->devices[0]->init(controller->devices[0]);
 239         uhci_reset(controller);
 240         uhci_reinit(controller);
 241         return controller;
 242 }
 243
 244 static void
 245 uhci_shutdown(hci_t *controller)
 246 {
 247         if (controller == 0)
 248                 return;
 249         detach_controller(controller);
 250         uhci_reg_write16(controller, USBCMD,
 251                          uhci_reg_read16(controller, USBCMD) & 0);      // stop work
 252         free(UHCI_INST(controller)->framelistptr);
 253         free(UHCI_INST(controller)->qh_prei);
 254         free(UHCI_INST(controller)->qh_intr);
 255         free(UHCI_INST(controller)->qh_data);
 256         free(UHCI_INST(controller)->qh_last);
 257         free(UHCI_INST(controller));
 258         free(controller);
 259 }
 260
 261 static void
 262 uhci_start(hci_t *controller)
 263 {
 264         uhci_reg_write16(controller, USBCMD,
 265                          uhci_reg_read16(controller, USBCMD) | 1);      // start work on schedule
 266 }
 267
 268 static void
 269 uhci_stop(hci_t *controller)
 270 {
 271         uhci_reg_write16(controller, USBCMD,
 272                          uhci_reg_read16(controller, USBCMD) & ~1);     // stop work on schedule
 273 }
 274
 275 #define UHCI_SLEEP_TIME_US 30
 276 #define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US)
 277 #define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
 278
 279 static td_t *
 280 wait_for_completed_qh(hci_t *controller, qh_t *qh)
 281 {
 282         int timeout = UHCI_TIMEOUT;
 283         void *current = GET_TD(qh->elementlinkptr);
 284         while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) {
 285                 if (current != GET_TD(qh->elementlinkptr)) {
 286                         current = GET_TD(qh->elementlinkptr);
 287                         timeout = UHCI_TIMEOUT;
 288                 }
 289                 uhci_reg_write16(controller, USBSTS,
 290                                  uhci_reg_read16(controller, USBSTS) | 0);      // clear resettable registers
 291                 udelay(UHCI_SLEEP_TIME_US);
 292         }
 293         return (GET_TD(qh->elementlinkptr) ==
 294                 0) ? 0 : GET_TD(phys_to_virt(qh->elementlinkptr));
 295 }
 296
 297 static int
 298 maxlen(int size)
 299 {
 300         return (size - 1) & 0x7ff;
 301 }
 302
 303 static int
 304 min(int a, int b)
 305 {
 306         if (a < b)
 307                 return a;
 308         else
 309                 return b;
 310 }
 311
 312 static int
 313 uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen,
 314               unsigned char *data)
 315 {
 316         int endp = 0;           /* this is control: always 0 */
 317         int mlen = dev->endpoints[0].maxpacketsize;
 318         int count = (2 + (dalen + mlen - 1) / mlen);
 319         unsigned short req = ((unsigned short *) devreq)[0];
 320         int i;
 321         td_t *tds = memalign(16, sizeof(td_t) * count);
 322         if (!tds)
 323                 fatal("Not enough memory for uhci control.\n");
 324         memset(tds, 0, sizeof(td_t) * count);
 325         count--;                /* to compensate for 0-indexed array */
 326         for (i = 0; i < count; i++) {
 327                 tds[i].ptr = virt_to_phys(&tds[i + 1]) | TD_DEPTH_FIRST;
 328         }
 329         tds[count].ptr = 0 | TD_DEPTH_FIRST | TD_TERMINATE;
 330
 331         tds[0].token = UHCI_SETUP |
 332                 dev->address << TD_DEVADDR_SHIFT |
 333                 endp << TD_EP_SHIFT |
 334                 TD_TOGGLE_DATA0 |
 335                 maxlen(drlen) << TD_MAXLEN_SHIFT;
 336         tds[0].bufptr = virt_to_phys(devreq);
 337         tds[0].ctrlsts = (3 << TD_COUNTER_SHIFT) |
 338                 (dev->speed?TD_LOWSPEED:0) |
 339                 TD_STATUS_ACTIVE;
 340
 341         int toggle = 1;
 342         for (i = 1; i < count; i++) {
 343                 switch (dir) {
 344                         case SETUP: tds[i].token = UHCI_SETUP; break;
 345                         case IN:    tds[i].token = UHCI_IN;    break;
 346                         case OUT:   tds[i].token = UHCI_OUT;   break;
 347                 }
 348                 tds[i].token |= dev->address << TD_DEVADDR_SHIFT |
 349                         endp << TD_EP_SHIFT |
 350                         maxlen(min(mlen, dalen)) << TD_MAXLEN_SHIFT |
 351                         toggle << TD_TOGGLE_SHIFT;
 352                 tds[i].bufptr = virt_to_phys(data);
 353                 tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) |
 354                         (dev->speed?TD_LOWSPEED:0) |
 355                         TD_STATUS_ACTIVE;
 356                 toggle ^= 1;
 357                 dalen -= mlen;
 358                 data += mlen;
 359         }
 360
 361         tds[count].token = ((dir == OUT) ? UHCI_IN : UHCI_OUT) |
 362                 dev->address << TD_DEVADDR_SHIFT |
 363                 endp << TD_EP_SHIFT |
 364                 maxlen(0) << TD_MAXLEN_SHIFT |
 365                 TD_TOGGLE_DATA1;
 366         tds[count].bufptr = 0;
 367         tds[count].ctrlsts = (0 << TD_COUNTER_SHIFT) | /* as Linux 2.4.10 does */
 368                 (dev->speed?TD_LOWSPEED:0) |
 369                 TD_STATUS_ACTIVE;
 370         UHCI_INST(dev->controller)->qh_data->elementlinkptr =
 371                 virt_to_phys(tds) & ~(FLISTP_QH | FLISTP_TERMINATE);
 372         td_t *td = wait_for_completed_qh(dev->controller,
 373                                           UHCI_INST(dev->controller)->
 374                                           qh_data);
 375         int result;
 376         if (td == 0) {
 377                 result = 0;
 378         } else {
 379                 usb_debug("control packet, req %x\n", req);
 380                 td_dump(td);
 381                 result = -1;
 382         }
 383         free(tds);
 384         return result;
 385 }
 386
 387 static td_t *
 388 create_schedule(int numpackets)
 389 {
 390         if (numpackets == 0)
 391                 return 0;
 392         td_t *tds = memalign(16, sizeof(td_t) * numpackets);
 393         if (!tds)
 394                 fatal("Not enough memory for packets scheduling.\n");
 395         memset(tds, 0, sizeof(td_t) * numpackets);
 396         int i;
 397         for (i = 0; i < numpackets; i++) {
 398                 tds[i].ptr = virt_to_phys(&tds[i + 1]) | TD_DEPTH_FIRST;
 399         }
 400         tds[numpackets - 1].ptr = 0 | TD_TERMINATE;
 401         return tds;
 402 }
 403
 404 static void
 405 fill_schedule(td_t *td, endpoint_t *ep, int length, unsigned char *data,
 406                int *toggle)
 407 {
 408         switch (ep->direction) {
 409                 case IN: td->token = UHCI_IN; break;
 410                 case OUT: td->token = UHCI_OUT; break;
 411                 case SETUP: td->token = UHCI_SETUP; break;
 412         }
 413         td->token |= ep->dev->address << TD_DEVADDR_SHIFT |
 414                 (ep->endpoint & 0xf) << TD_EP_SHIFT |
 415                 maxlen(length) << TD_MAXLEN_SHIFT |
 416                 (*toggle & 1) << TD_TOGGLE_SHIFT;
 417         td->bufptr = virt_to_phys(data);
 418         td->ctrlsts = ((ep->direction == SETUP?3:0) << TD_COUNTER_SHIFT) |
 419                 (ep->dev->speed?TD_LOWSPEED:0) |
 420                 TD_STATUS_ACTIVE;
 421         *toggle ^= 1;
 422 }
 423
 424 static int
 425 run_schedule(usbdev_t *dev, td_t *td)
 426 {
 427         UHCI_INST(dev->controller)->qh_data->elementlinkptr =
 428                 virt_to_phys(td) & ~(FLISTP_QH | FLISTP_TERMINATE);
 429         td = wait_for_completed_qh(dev->controller,
 430                                     UHCI_INST(dev->controller)->qh_data);
 431         if (td == 0) {
 432                 return 0;
 433         } else {
 434                 td_dump(td);
 435                 return 1;
 436         }
 437 }
 438
 439 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
 440 static int
 441 uhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize)
 442 {
 443         int maxpsize = ep->maxpacketsize;
 444         if (maxpsize == 0)
 445                 fatal("MaxPacketSize == 0!!!");
 446         int numpackets = (size + maxpsize - 1) / maxpsize;
 447         if (finalize && ((size % maxpsize) == 0)) {
 448                 numpackets++;
 449         }
 450         if (numpackets == 0)
 451                 return 0;
 452         td_t *tds = create_schedule(numpackets);
 453         int i = 0, toggle = ep->toggle;
 454         while ((size > 0) || ((size == 0) && (finalize != 0))) {
 455                 fill_schedule(&tds[i], ep, min(size, maxpsize), data,
 456                                &toggle);
 457                 i++;
 458                 data += maxpsize;
 459                 size -= maxpsize;
 460         }
 461         if (run_schedule(ep->dev, tds) == 1) {
 462                 free(tds);
 463                 return -1;
 464         }
 465         ep->toggle = toggle;
 466         free(tds);
 467         return 0;
 468 }
 469
 470 typedef struct {
 471         qh_t *qh;
 472         td_t *tds;
 473         td_t *last_td;
 474         u8 *data;
 475         int lastread;
 476         int total;
 477         int reqsize;
 478 } intr_q;
 479
 480 /* create and hook-up an intr queue into device schedule */
 481 static void*
 482 uhci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming)
 483 {
 484         u8 *data = malloc(reqsize*reqcount);
 485         td_t *tds = memalign(16, sizeof(td_t) * reqcount);
 486         qh_t *qh = memalign(16, sizeof(qh_t));
 487
 488         if (!data || !tds || !qh)
 489                 fatal("Not enough memory to create USB intr queue prerequisites.\n");
 490
 491         qh->elementlinkptr = virt_to_phys(tds);
 492
 493         intr_q *q = malloc(sizeof(intr_q));
 494         if (!q)
 495                 fatal("Not enough memory to create USB intr queue.\n");
 496         q->qh = qh;
 497         q->tds = tds;
 498         q->data = data;
 499         q->lastread = 0;
 500         q->total = reqcount;
 501         q->reqsize = reqsize;
 502         q->last_td = &tds[reqcount - 1];
 503
 504         memset(tds, 0, sizeof(td_t) * reqcount);
 505         int i;
 506         for (i = 0; i < reqcount; i++) {
 507                 tds[i].ptr = virt_to_phys(&tds[i + 1]);
 508
 509                 switch (ep->direction) {
 510                         case IN: tds[i].token = UHCI_IN; break;
 511                         case OUT: tds[i].token = UHCI_OUT; break;
 512                         case SETUP: tds[i].token = UHCI_SETUP; break;
 513                 }
 514                 tds[i].token |= ep->dev->address << TD_DEVADDR_SHIFT |
 515                         (ep->endpoint & 0xf) << TD_EP_SHIFT |
 516                         maxlen(reqsize) << TD_MAXLEN_SHIFT |
 517                         (ep->toggle & 1) << TD_TOGGLE_SHIFT;
 518                 tds[i].bufptr = virt_to_phys(data);
 519                 tds[i].ctrlsts = (0 << TD_COUNTER_SHIFT) |
 520                         (ep->dev->speed?TD_LOWSPEED:0) |
 521                         TD_STATUS_ACTIVE;
 522                 ep->toggle ^= 1;
 523                 data += reqsize;
 524         }
 525         tds[reqcount - 1].ptr = 0 | TD_TERMINATE;
 526
 527         /* insert QH into framelist */
 528         uhci_t *const uhcic = UHCI_INST(ep->dev->controller);
 529         const u32 def_ptr = virt_to_phys(uhcic->qh_prei) | FLISTP_QH;
 530         int nothing_placed = 1;
 531         qh->headlinkptr = def_ptr;
 532         for (i = 0; i < 1024; i += reqtiming) {
 533                 /* advance to the next free position */
 534                 while ((i < 1024) && (uhcic->framelistptr[i] != def_ptr)) ++i;
 535                 if (i < 1024) {
 536                         uhcic->framelistptr[i] = virt_to_phys(qh) | FLISTP_QH;
 537                         nothing_placed = 0;
 538                 }
 539         }
 540         if (nothing_placed) {
 541                 usb_debug("Error: Failed to place UHCI interrupt queue "
 542                               "head into framelist: no space left\n");
 543                 uhci_destroy_intr_queue(ep, q);
 544                 return NULL;
 545         }
 546
 547         return q;
 548 }
 549
 550 /* remove queue from device schedule, dropping all data that came in */
 551 static void
 552 uhci_destroy_intr_queue(endpoint_t *ep, void *q_)
 553 {
 554         intr_q *const q = (intr_q*)q_;
 555
 556         /* remove QH from framelist */
 557         uhci_t *const uhcic = UHCI_INST(ep->dev->controller);
 558         const u32 qh_ptr = virt_to_phys(q->qh) | FLISTP_QH;
 559         const u32 def_ptr = virt_to_phys(uhcic->qh_prei) | FLISTP_QH;
 560         int i;
 561         for (i = 0; i < 1024; ++i) {
 562                 if (uhcic->framelistptr[i] == qh_ptr)
 563                         uhcic->framelistptr[i] = def_ptr;
 564         }
 565
 566         free(q->data);
 567         free(q->tds);
 568         free(q->qh);
 569         free(q);
 570 }
 571
 572 /* read one intr-packet from queue, if available. extend the queue for new input.
 573    return NULL if nothing new available.
 574    Recommended use: while (data=poll_intr_queue(q)) process(data);
 575  */
 576 static u8*
 577 uhci_poll_intr_queue(void *q_)
 578 {
 579         intr_q *q = (intr_q*)q_;
 580         if ((q->tds[q->lastread].ctrlsts & TD_STATUS_ACTIVE) == 0) {
 581                 int current = q->lastread;
 582                 int previous;
 583                 if (q->lastread == 0) {
 584                         previous = q->total - 1;
 585                 } else {
 586                         previous = q->lastread - 1;
 587                 }
 588                 q->tds[previous].ctrlsts &= ~TD_STATUS_MASK;
 589                 q->tds[previous].ptr = 0 | TD_TERMINATE;
 590                 if (q->last_td != &q->tds[previous]) {
 591                         q->last_td->ptr = virt_to_phys(&q->tds[previous]) & ~TD_TERMINATE;
 592                         q->last_td = &q->tds[previous];
 593                 }
 594                 q->tds[previous].ctrlsts |= TD_STATUS_ACTIVE;
 595                 q->lastread = (q->lastread + 1) % q->total;
 596                 if (!(q->tds[current].ctrlsts & TD_STATUS_MASK))
 597                         return &q->data[current*q->reqsize];
 598         }
 599         /* reset queue if we fully processed it after underrun */
 600         else if (q->qh->elementlinkptr & FLISTP_TERMINATE) {
 601                 usb_debug("resetting underrun uhci interrupt queue.\n");
 602                 q->qh->elementlinkptr = virt_to_phys(q->tds + q->lastread);
 603         }
 604         return NULL;
 605 }
 606
 607 void
 608 uhci_reg_write32(hci_t *ctrl, usbreg reg, u32 value)
 609 {
 610         outl(value, ctrl->reg_base + reg);
 611 }
 612
 613 u32
 614 uhci_reg_read32(hci_t *ctrl, usbreg reg)
 615 {
 616         return inl(ctrl->reg_base + reg);
 617 }
 618
 619 void
 620 uhci_reg_write16(hci_t *ctrl, usbreg reg, u16 value)
 621 {
 622         outw(value, ctrl->reg_base + reg);
 623 }
 624
 625 u16
 626 uhci_reg_read16(hci_t *ctrl, usbreg reg)
 627 {
 628         return inw(ctrl->reg_base + reg);
 629 }
 630
 631 void
 632 uhci_reg_write8(hci_t *ctrl, usbreg reg, u8 value)
 633 {
 634         outb(value, ctrl->reg_base + reg);
 635 }
 636
 637 u8
 638 uhci_reg_read8(hci_t *ctrl, usbreg reg)
 639 {
 640         return inb(ctrl->reg_base + reg);
 641 }