src/mainboard/acer/aspire_vn7_572g/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <gpio.h>
   4 #include "include/gpio.h"
   5
   6 /*
   7  * TODO: Vendor configures many NC pads as _TERM_GPO. Why?
   8  * - On direction: Are some of these comments illusory? At least some pads
   9  *   are bidirectional on the other side of the GPIO.
  10  */
  11 /* NB: Do not reconfigure pads used by Optimus, their assertion state may be lost */
  12
  13 /*
  14  * TODO: Newgate-SLS and Rayleigh-SLS have PCH-H and use the same ProgramGPIOPei module.
  15  *       The GPIO tables retrieved from PCDs are ignored. However, progress on those SKUs
  16  *       is held up because the final table passed to function similar to RC's
  17  *       GpioConfigureSklPch() is neither, but a zero-assigned variable. The code may be
  18  *       computing and dereferencing address pointers from a blob of internal data.
  19  */
  20
  21 /* Pad configuration was generated automatically using intelp2m utility */
  22 static const struct pad_config gpio_table[] = {
  23
  24         /* ------- GPIO Community 0 ------- */
  25
  26         /* ------- GPIO Group GPP_A ------- */
  27         // RCIN# <= H_RCIN#
  28         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  29         // LAD0 (ESPI_IO0) <=> LPC_AD_CPU_P0
  30         PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
  31         // LAD1 (ESPI_IO1) <=> LPC_AD_CPU_P1
  32         PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
  33         // LAD2 (ESPI_IO2) <=> LPC_AD_CPU_P2
  34         PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
  35         // LAD3 (ESPI_IO3) <=> LPC_AD_CPU_P3
  36         PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
  37         // LFRAME# (ESPI_CS#) => LPC_FRAME#_CPU
  38         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  39         // SERIRQ <=> INT_SERIRQ
  40         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  41         // PIRQA# = PIRQA#
  42         PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
  43         // CLKRUN# <= PM_CLKRUN#_EC
  44         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  45         // CLKOUT_LPC0 (ESPI_CLK) <= LPC_CLK_CPU_P0
  46         PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
  47         // CLKOUT_LPC1 <= LPC_CLK_CPU_P1
  48         PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
  49         // GPIO (PME#) // NC
  50         PAD_CFG_TERM_GPO(GPP_A11, 1, DN_20K, DEEP),
  51         // GPIO (SX_EXIT_HOLDOFF#/BM_BUSY#/ISH_GP6) <= GC6_FB_EN
  52         PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI),
  53         // SUSWARN#/SUSPWRDNACK = PM_SUSACK#
  54         PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  55         // SUS_STAT# (ESPI_RESET#) => PM_SUS_STAT#
  56         PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
  57         // SUS_ACK# = PM_SUSACK#
  58         PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
  59         // GPIO (SD_1P8_SEL) // NC
  60         PAD_NC(GPP_A16, DN_20K),
  61         // GPIO (SD_PWR_EN#/ISH_GP7) // NC
  62         PAD_NC(GPP_A17, DN_20K),
  63         // GPIO (ISH_GP0) => GSENSOR_INT#
  64         PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, ACPI),
  65         // GPIO (ISH_GP1) // NC
  66         PAD_NC(GPP_A19, DN_20K),
  67         // GPIO (ISH_GP3) // NC
  68         PAD_NC(GPP_A21, DN_20K),
  69         // GPIO (ISH_GP4) <= GPU_EVENT#
  70         PAD_CFG_GPO(GPP_A22, 1, DEEP),
  71         // GPIO (ISH_GP5) // NC
  72         PAD_NC(GPP_A23, DN_20K),
  73
  74         /* ------- GPIO Group GPP_B ------- */
  75         // CORE_VID0 // V0.85A_VID0
  76         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  77         // CORE_VID1 // V0.85A_VID1
  78         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  79         // GPIO (CPU_GP2) <= TP_IN#
  80         // TODO: APIC-routed pads don't have host owners?
  81         PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP),
  82         // SRCCLKREQ0# <= PEG_CLKREQ_CPU#
  83         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  84         // SRCCLKREQ1# <= LAN_CLKREQ_CPU#
  85         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  86         // SRCCLKREQ2# <= WLAN_CLKREQ_CPU#
  87         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  88         // SRCCLKREQ3# <= MSATA_CLKREQ_CPU#
  89         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  90         // SRCCLKREQ4# // SRCCLKREQ4# ("Remove TBT")
  91         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  92         // SRCCLKREQ5# // SRCCLKREQ5#
  93         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  94         // GPIO (EXT_PWR_GATE#) = EXT_PWR_GATE#
  95         PAD_CFG_TERM_GPO(GPP_B11, 1, DN_20K, DEEP),
  96         // GPIO (SLP_S0#) // NC
  97         PAD_CFG_TERM_GPO(GPP_B12, 1, DN_20K, DEEP),
  98         // PLTRST# => PLT_RST#
  99         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 100         // GPIO (SPKR) => HDA_SPKR (Strap - Top Swap Override)
 101         PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
 102         // GPIO (GSPI0_CS#) = TOUCH_DET#
 103         PAD_CFG_GPO(GPP_B15, 0, DEEP),
 104         // GPIO (GSPI0_CLK) // NC
 105         PAD_CFG_GPO(GPP_B16, 0, DEEP),
 106         // GPIO (GSPI0_MISO) // NC ("Remove TBT")
 107         PAD_CFG_GPI_SCI(GPP_B17, DN_20K, DEEP, EDGE_SINGLE, INVERT),
 108         // GPIO (GSPI0_MOSI) => GPP_B18/GSPI0_MOSI (Strap - No reboot)
 109         PAD_CFG_TERM_GPO(GPP_B18, 1, DN_20K, DEEP),
 110         // GPIO (GSPI1_CS#) => RTC_DET#
 111         PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI),
 112         // GPIO (GSPI1_CLK) <= PSW_CLR#
 113         PAD_CFG_GPI_TRIG_OWN(GPP_B20, DN_20K, DEEP, OFF, ACPI),
 114         // GPIO (GSPI1_MOSI) => GPP_B22/GSPI1_MOSI (Strap - Boot BIOS strap)
 115         PAD_CFG_TERM_GPO(GPP_B22, 1, DN_20K, DEEP),
 116         // GPIO (SML1ALERT#/PCHHOT#) => GPP_B23 (Strap)
 117         PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
 118
 119         /* ------- GPIO Community 1 ------- */
 120
 121         /* ------- GPIO Group GPP_C ------- */
 122         // SMBCLK <= SMB_CLK
 123         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 124         // SMBDATA = SMB_DATA
 125         PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
 126         // GPIO (SMBALERT#) => GPP_C2 (Strap - TLS Confidentiality)
 127         PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
 128         // GPIO (SML0CLK) // NC
 129         PAD_CFG_TERM_GPO(GPP_C3, 1, DN_20K, DEEP),
 130         // GPIO (SML0DATA) // NC
 131         PAD_CFG_TERM_GPO(GPP_C4, 1, DN_20K, DEEP),
 132         // GPIO (SML0ALERT#) // NC (Strap - eSPI or LPC)
 133         PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, DEEP),
 134         // RESERVED (SML1CLK) <=> SML1_CLK (KBC)
 135         // RESERVED (SML1DATA) <=> SML1_DATA (KBC)
 136         // GPIO (UART0_RXD) // NC
 137         PAD_CFG_TERM_GPO(GPP_C8, 1, DN_20K, DEEP),
 138         // GPIO (UART0_TXD) // NC
 139         PAD_CFG_TERM_GPO(GPP_C9, 1, DN_20K, DEEP),
 140         // GPIO (UART0_RTS#) // NC
 141         PAD_CFG_TERM_GPO(GPP_C10, 1, DN_20K, DEEP),
 142         // GPIO (UART0_CTS#) // NC
 143         PAD_CFG_TERM_GPO(GPP_C11, 1, DN_20K, DEEP),
 144         // GPIO (UART1_RXD/ISH_UART1_RXD) // NC
 145         PAD_NC(GPP_C12, DN_20K),
 146         // GPIO (UART1_TXD/ISH_UART1_TXD) // NC
 147         PAD_NC(GPP_C13, DN_20K),
 148         // GPIO (UART1_RTS#/ISH_UART1_RTS#) // NC
 149         PAD_NC(GPP_C14, DN_20K),
 150         // GPIO (UART1_CTS#/ISH_UART1_CTS#) // NC
 151         PAD_NC(GPP_C15, DN_20K),
 152         // I2C0_SDA <=> I2C0_DATA_CPU (Touch Panel)
 153         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 154         // I2C0_SCL <=> I2C0_CLK_CPU (Touch Panel)
 155         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 156         // I2C1_SDA <=> I2C1_DATA_CPU (Touch Pad)
 157         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 158         // I2C1_SCL <=> I2C1_CLK_CPU (Touch Pad)
 159         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 160         // UART2_RXD = LPSS_UART2_RXD
 161         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 162         // UART2_TXD = LPSS_UART2_TXD
 163         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 164         // UART2_RTS# = LPSS_UART2_RTS#
 165         PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 166         // UART2_CTS# = LPSS_UART2_CTS#
 167         PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 168
 169         /* ------- GPIO Group GPP_D ------- */
 170         // GPIO (SPI1_CS#) // NC
 171         PAD_CFG_TERM_GPO(GPP_D0, 1, DN_20K, DEEP),
 172         // GPIO (SPI1_CLK) // NC
 173         PAD_CFG_TERM_GPO(GPP_D1, 1, DN_20K, DEEP),
 174         // SPI1_MISO // NC
 175         PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
 176         // SPI1_MOSI // NC
 177         PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
 178         // GPIO (FLASHTRIG) // NC
 179         PAD_CFG_TERM_GPO(GPP_D4, 1, DN_20K, DEEP),
 180         // GPIO (ISH_I2C0_SDA) // NC
 181         PAD_NC(GPP_D5, DN_20K),
 182         // GPIO (ISH_I2C0_SCL) // NC
 183         PAD_NC(GPP_D6, DN_20K),
 184         // GPIO (ISH_I2C1_SDA) // NC
 185         PAD_NC(GPP_D7, DN_20K),
 186         // GPIO (ISH_I2C1_SCL) // NC
 187         PAD_NC(GPP_D8, DN_20K),
 188         // GPIO // NC
 189         PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
 190         // GPIO => TOUCH_S_RST#
 191         PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
 192         // GPIO // NC
 193         PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
 194         // GPIO // NC ("Remove TBT")
 195         PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
 196         // GPIO (ISH_UART0_RXD/SML0BDATA/I2C4B_SDA) // NC
 197         PAD_CFG_TERM_GPO(GPP_D13, 1, DN_20K, DEEP),
 198         // GPIO (ISH_UART0_TXD/SML0BCLK/I2C4B_SCL) // NC
 199         PAD_CFG_TERM_GPO(GPP_D14, 1, DN_20K, DEEP),
 200         // GPIO (ISH_UART0_RTS#) // NC
 201         PAD_CFG_TERM_GPO(GPP_D15, 1, DN_20K, DEEP),
 202         // GPIO (ISH_UART0_CTS#/SML0BALERT#) // NC
 203         PAD_CFG_TERM_GPO(GPP_D16, 1, DN_20K, DEEP),
 204         // GPIO (DMIC_CLK1) // NC
 205         PAD_NC(GPP_D17, DN_20K),
 206         // GPIO (DMIC_DATA1) // NC
 207         PAD_NC(GPP_D18, DN_20K),
 208         // DMIC_CLK0 => DMIC_CLK_CON_R
 209         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 210         // DMIC_DATA0 => DMIC_PCH_DATA
 211         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 212         // SPI1_IO2 // NC
 213         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 214         // SPI1_IO3 // NC
 215         PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 216         // GPIO (I2S_MCLK) // NC
 217         PAD_NC(GPP_D23, DN_20K),
 218
 219         /* ------- GPIO Group GPP_E ------- */
 220         // SATAXPCIE0 (SATAGP0) = SATAGP0
 221         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
 222         // SATAXPCIE1 (SATAGP1) // NC
 223         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 224         // SATAXPCIE2 (SATAGP2) = SATAGP2
 225         PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
 226         // GPIO (CPU_GP0) // NC
 227         PAD_CFG_GPO(GPP_E3, 1, DEEP),
 228         // GPIO (DEVSLP0) // NC ("Remove DEVSLP_PCH")
 229         PAD_CFG_TERM_GPO(GPP_E4, 1, DN_20K, DEEP),
 230         // GPIO (DEVSLP1) // NC
 231         PAD_CFG_TERM_GPO(GPP_E5, 1, DN_20K, DEEP),
 232         // GPIO (DEVSLP2) // NC
 233         PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, DEEP),
 234         // GPIO (CPU_GP1) <= TOUCH_INT#
 235         PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, DEEP),
 236         // SATALED# = SATA_LED#
 237         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 238         // USB2_OC0# = USB_OC#
 239         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 240         // USB2_OC1# // USB_OC#
 241         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 242         // USB2_OC2# // USB_OC#
 243         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 244         // USB2_OC3# // USB_OC#
 245         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 246         // DDPB_HPD0 <= DDI1_HDMI_HPD_CPU
 247         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 248         // DDPC_HPD1 // NC ("Remove HPD")
 249         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 250         // GPIO (DDPD_HPD2) <= EC_SMI#
 251         // FIXME: Vendor configures as _TERM_GPO. Why?
 252         PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, LEVEL, INVERT),
 253         // GPIO (DDPE_HPD3) <= EC_SCI#
 254         PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
 255         // EDP_HPD <= eDP_HPD_CPU
 256         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 257         // DDPB_CTRLCLK <=> DDI1_HDMI_CLK_CPU
 258         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 259         // DDPB_CTRLDATA <=> DDI1_HDMI_DATA_CPU (Strap - Display Port B Detected)
 260         PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
 261         // DDPC_CTRLCLK // NC
 262         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 263         // DDPC_CTRLDATA => DDPC_CDA (Strap - Display Port C Detected)
 264         PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
 265         // GPIO // NC
 266         // TODO: Vendor configures as _GPIO_BIDIRECT. Why?
 267         PAD_NC(GPP_E22, NONE),
 268         // GPIO => DDPD_CDA (Strap - Display Port D Detected)
 269         PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
 270
 271         /* ------- GPIO Community 2 ------- */
 272
 273         /* -------- GPIO Group GPD -------- */
 274         // GPIO (BATLOW#) = BATLOW
 275         PAD_CFG_TERM_GPO(GPD0, 1, DN_20K, PWROK),
 276         // ACPRESENT <= AC_PRESENT
 277         PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
 278         // GPIO (LAN_WAKE#) = GPD2/LAN_WAKE#
 279         PAD_CFG_TERM_GPO(GPD2, 1, DN_20K, PWROK),
 280         // PWRBTN# <= PM_PWRBTN#
 281         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
 282         // SLP_S3# => PM_SLP_S3#
 283         PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
 284         // SLP_S4# => PM_SLP_S4#
 285         PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
 286         // SLP_A# // NC
 287         PAD_CFG_NF(GPD6, DN_20K, PWROK, NF1),
 288         // GPIO (RSVD#AT15) // NC
 289         PAD_CFG_TERM_GPO(GPD7, 1, DN_20K, PWROK),
 290         // SUSCLK => SUS_CLK_CPU
 291         PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 292         // SLP_WLAN# // NC
 293         PAD_CFG_NF(GPD9, DN_20K, PWROK, NF1),
 294         // SLP_S5# // NC
 295         PAD_CFG_NF(GPD10, DN_20K, PWROK, NF1),
 296         // GPIO (LANPHYPC) // NC
 297         PAD_CFG_TERM_GPO(GPD11, 1, DN_20K, PWROK),
 298
 299         /* ------- GPIO Community 3 ------- */
 300
 301         /* ------- GPIO Group GPP_F ------- */
 302         // GPIO (I2S2_SCLK) // NC
 303         PAD_NC(GPP_F0, DN_20K),
 304         // GPIO (I2S2_SFRM) // NC
 305         PAD_NC(GPP_F1, DN_20K),
 306         // GPIO (I2S2_TXD) // NC
 307         PAD_NC(GPP_F2, DN_20K),
 308         // GPIO (I2S2_RXD) // NC
 309         PAD_NC(GPP_F3, DN_20K),
 310         // GPIO (I2C2_SDA) // NC
 311         PAD_NC(GPP_F4, DN_20K),
 312         // GPIO (I2C2_SCL) // NC
 313         PAD_NC(GPP_F5, DN_20K),
 314         // GPIO (I2C3_SDA) // NC
 315         PAD_NC(GPP_F6, DN_20K),
 316         // GPIO (I2C3_SCL) // NC
 317         PAD_NC(GPP_F7, DN_20K),
 318         // GPIO (I2C4_SDA) // NC
 319         PAD_CFG_TERM_GPO(GPP_F8, 1, DN_20K, DEEP),
 320         // GPIO (I2C4_SCL) // NC
 321         PAD_CFG_TERM_GPO(GPP_F9, 1, DN_20K, DEEP),
 322         // GPIO (I2C5_SDA/ISH_I2C2_SDA) // NC
 323         PAD_NC(GPP_F10, DN_20K),
 324         // GPIO (I2C5_SCL/ISH_I2C2_SCL) // NC
 325         PAD_NC(GPP_F11, DN_20K),
 326         // GPIO (EMMC_CMD) // NC
 327         PAD_NC(GPP_F12, DN_20K),
 328         // GPIO (EMMC_DATA0) // NC
 329         PAD_NC(GPP_F13, DN_20K),
 330         // GPIO (EMMC_DATA1) // NC
 331         PAD_NC(GPP_F14, DN_20K),
 332         // GPIO (EMMC_DATA2) // NC
 333         PAD_NC(GPP_F15, DN_20K),
 334         // GPIO (EMMC_DATA3) // NC
 335         PAD_NC(GPP_F16, DN_20K),
 336         // GPIO (EMMC_DATA4) // NC
 337         PAD_NC(GPP_F17, DN_20K),
 338         // GPIO (EMMC_DATA5) // NC
 339         PAD_NC(GPP_F18, DN_20K),
 340         // GPIO (EMMC_DATA6) // NC
 341         PAD_NC(GPP_F19, DN_20K),
 342         // GPIO (EMMC_DATA7) // NC
 343         PAD_NC(GPP_F20, DN_20K),
 344         // GPIO (EMMC_RCLK) // NC
 345         PAD_NC(GPP_F21, DN_20K),
 346         // GPIO (EMMC_CLK) // NC
 347         PAD_NC(GPP_F22, DN_20K),
 348         // GPIO // NC
 349         PAD_CFG_GPI_APIC_HIGH(GPP_F23, NONE, DEEP),
 350
 351         /* ------- GPIO Group GPP_G ------- */
 352         // GPIO (SD_CMD) // NC
 353         PAD_NC(GPP_G0, DN_20K),
 354         // GPIO (SD_DATA0) // NC
 355         PAD_NC(GPP_G1, DN_20K),
 356         // GPIO (SD_DATA1) // NC
 357         PAD_NC(GPP_G2, DN_20K),
 358         // GPIO (SD_DATA2) // NC
 359         PAD_NC(GPP_G3, DN_20K),
 360         // GPIO (SD_DATA3) // NC
 361         // TODO: Vendor configures as _GPO. Why?
 362         PAD_NC(GPP_G4, NONE),
 363         // GPIO (SD_CD#) // NC
 364         PAD_NC(GPP_G5, DN_20K),
 365         // GPIO (SD_CLK) // NC
 366         PAD_NC(GPP_G6, DN_20K),
 367         // GPIO (SD_WP) // NC
 368         PAD_NC(GPP_G7, DN_20K),
 369 };
 370
 371 void mainboard_config_stage_gpios(void)
 372 {
 373         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 374 }