src/mainboard/amd/gardenia/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <amdblocks/agesawrapper.h>
   5 #include <amdblocks/amd_pci_util.h>
   6 #include <gpio.h>
   7 #include <soc/southbridge.h>
   8
   9 #include "gpio.h"
  10
  11 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  12    accessed via I/O ports 0xc00/0xc01. */
  13 static const struct fch_irq_routing fch_irq_map[] = {
  14         { PIRQ_A,        3,             16 },
  15         { PIRQ_B,        4,             17 },
  16         { PIRQ_C,        5,             18 },
  17         { PIRQ_D,        7,             19 },
  18         { PIRQ_E,       11,             20 },
  19         { PIRQ_F,       10,             21 },
  20         { PIRQ_G,       PIRQ_NC,        22 },
  21         { PIRQ_H,       PIRQ_NC,        23 },
  22         { PIRQ_SCI,     PIRQ_NC,         9 },
  23         { PIRQ_SMBUS,   PIRQ_NC,        PIRQ_NC },
  24         { PIRQ_HDA,      3,             16 },
  25         { PIRQ_SD,      PIRQ_NC,        16 },
  26         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  27         { PIRQ_EHCI,     5,             18 },
  28         { PIRQ_XHCI,     4,             18 },
  29         { PIRQ_SATA,    PIRQ_NC,        19 },
  30         { PIRQ_GPIO,     7,              7 },
  31         { PIRQ_I2C0,     3,              3 },
  32         { PIRQ_I2C1,    15,             15 },
  33         { PIRQ_I2C2,     6,              6 },
  34         { PIRQ_I2C3,    14,             14 },
  35         { PIRQ_UART0,   10,             10 },
  36         { PIRQ_UART1,   11,             11 },
  37
  38         /* The MISC registers are not interrupt numbers */
  39         { PIRQ_MISC,    0xfa,   0x00 },
  40         { PIRQ_MISC0,   0xf1,   0x00 },
  41         { PIRQ_MISC1,   0x00,   0x00 },
  42         { PIRQ_MISC2,   0x00,   0x00 },
  43 };
  44
  45 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  46 {
  47         *length = ARRAY_SIZE(fch_irq_map);
  48         return fch_irq_map;
  49 }
  50
  51 static void mainboard_init(void *chip_info)
  52 {
  53         size_t num_gpios;
  54         const struct soc_amd_gpio *gpios;
  55         gpios = gpio_table(&num_gpios);
  56         gpio_configure_pads(gpios, num_gpios);
  57 }
  58
  59 struct chip_operations mainboard_ops = {
  60         .init = mainboard_init,
  61 };