src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/skylake
   4         register "panel_cfg" = "{
   5                 .up_delay_ms            = 200,  // T3
   6                 .down_delay_ms          =   0,  // T10
   7                 .cycle_delay_ms         = 500,  // T12
   8                 .backlight_on_delay_ms  =  50,  // T7
   9                 .backlight_off_delay_ms =   0,  // T9
  10                 .backlight_pwm_hz       = 200,
  11         }"
  12
  13         # IGD Displays
  14         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
  15
  16         # FSP Configuration
  17         register "SkipExtGfxScan" = "1"
  18         register "SaGv" = "SaGv_Enabled"
  19         register "eist_enable" = "1"
  20
  21         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  22         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  23         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  24         register "PmConfigSlpAMinAssert" = "3"          # 2s
  25
  26         # Send an extra VR mailbox command for the PS4 exit issue
  27         register "SendVrMbxCmd" = "2"
  28
  29         register "power_limits_config" = "{
  30                 .tdp_pl1_override = 20,
  31                 .tdp_pl2_override = 30,
  32         }"
  33
  34         register "SerialIoDevMode" = "{
  35                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
  36         }"
  37
  38         device cpu_cluster 0 on end
  39         device domain 0 on
  40                 subsystemid 0x1558 0x1313 inherit
  41                 device ref system_agent on      end
  42                 device ref igpu         on      end
  43                 device ref sa_thermal   on      end
  44                 device ref south_xhci   on
  45                         register "SsicPortEnable" = "0"
  46                         # USB2
  47                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A, right
  48                         register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"    # 3G / LTE
  49                         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # Type-C, right
  50                         register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"    # Camera
  51                         register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"    # Bluetooth
  52                         register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"    # Type-A, left
  53                         register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # Type-C, right
  54                         # USB3
  55                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right
  56                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
  57                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
  58                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
  59                 end
  60                 device ref thermal      on      end
  61                 device ref heci1        on      end
  62                 device ref sata         on
  63                         register "SataSalpSupport" = "0"
  64                         # Ports
  65                         register "SataPortsEnable[0]" = "1"
  66                         register "SataPortsEnable[2]" = "1"
  67                         register "SataPortsDevSlp[2]" = "1"
  68                 end
  69                 device ref uart2        on      end
  70                 device ref pcie_rp1     on
  71                         device pci 00.0 on end # x4 TBT
  72                         register "PcieRpEnable[0]" = "1"
  73                         register "PcieRpClkReqSupport[0]" = "1"
  74                         register "PcieRpClkReqNumber[0]" = "4"
  75                         register "PcieRpClkSrcNumber[0]" = "4"
  76                         register "PcieRpHotPlug[0]" = "1"
  77                         register "PcieRpLtrEnable[0]" = "1"
  78                         smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
  79                 end
  80                 device ref pcie_rp5     on
  81                         device pci 00.0 on end # x1 LAN
  82                         register "PcieRpEnable[4]" = "1"
  83                         register "PcieRpClkReqSupport[4]" = "1"
  84                         register "PcieRpClkReqNumber[4]" = "3"
  85                         register "PcieRpClkSrcNumber[4]" = "3"
  86                         register "PcieRpLtrEnable[4]" = "1"
  87                 end
  88                 device ref pcie_rp6     on
  89                         device pci 00.0 on end # x1 WLAN
  90                         register "PcieRpEnable[5]" = "1"
  91                         register "PcieRpClkReqSupport[5]" = "1"
  92                         register "PcieRpClkReqNumber[5]" = "2"
  93                         register "PcieRpClkSrcNumber[5]" = "2"
  94                         register "PcieRpLtrEnable[5]" = "1"
  95                         smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
  96                 end
  97                 device ref pcie_rp9     on
  98                         device pci 00.0 on end # x4 M.2/M (J_SSD1)
  99                         register "PcieRpEnable[8]" = "1"
 100                         register "PcieRpClkReqSupport[8]" = "1"
 101                         register "PcieRpClkReqNumber[8]" = "5"
 102                         register "PcieRpClkSrcNumber[8]" = "5"
 103                         register "PcieRpLtrEnable[8]" = "1"
 104                         smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
 105                 end
 106                 device ref lpc_espi     on
 107                         register "gen1_dec" = "0x000c0681"
 108                         register "gen2_dec" = "0x000c1641"
 109                         register "gen3_dec" = "0x00040069"
 110                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 111                         chip drivers/pc80/tpm
 112                                 device pnp 0c31.0 on end
 113                         end
 114                 end
 115                 device ref p2sb         hidden  end
 116                 device ref pmc          on
 117                         register "gpe0_dw0" = "GPP_C"
 118                         register "gpe0_dw1" = "GPP_D"
 119                         register "gpe0_dw2" = "GPP_E"
 120                 end
 121                 device ref hda          on      end
 122                 device ref smbus        on      end
 123                 device ref fast_spi     on      end
 124         end
 125 end