src/mainboard/google/link/devicetree.cb

   1 chip northbridge/intel/sandybridge
   2         # IGD Displays
   3         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   4
   5         # Enable DisplayPort Hotplug with 6ms pulse
   6         register "gpu_dp_d_hotplug" = "0x06"
   7
   8         # Enable Panel as eDP and configure power delays
   9         register "gpu_panel_port_select" = "PANEL_PORT_DP_A"
  10         register "gpu_panel_power_cycle_delay" = "6"            # 500ms
  11         register "gpu_panel_power_up_delay" = "2000"            # 200ms
  12         register "gpu_panel_power_down_delay" = "500"           # 50ms
  13         register "gpu_panel_power_backlight_on_delay" = "2000"  # 200ms
  14         register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
  15
  16         # Set backlight PWM values for eDP
  17         register "gpu_cpu_backlight" = "0x00000200"
  18         register "gpu_pch_backlight" = "0x04000000"
  19
  20         register "max_mem_clock_mhz" = "666"
  21
  22         device domain 0 on
  23                 subsystemid 0x1ae0 0xc000 inherit
  24                 device ref host_bridge on end # host bridge
  25                 device ref igd on end # vga controller
  26
  27                 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
  28                         # GPI routing
  29                         #  0 No effect (default)
  30                         #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  31                         #  2 SCI (if corresponding GPIO_EN bit is also set)
  32                         register "alt_gp_smi_en" = "0x0100"
  33                         register "gpi7_routing" = "2"
  34                         register "gpi8_routing" = "1"
  35
  36                         register "sata_port_map" = "0x1"
  37
  38                         register "sata_port0_gen3_tx" = "0x00880a7f"
  39
  40                         # EC range is 0x800-0x9ff
  41                         # Please note: you MUST not change this unless
  42                         # you also change romstage.c:pch_enable_lpc
  43                         register "gen1_dec" = "0x00fc0801"
  44                         register "gen2_dec" = "0x00fc0901"
  45
  46                         # Enable zero-based linear PCIe root port functions
  47                         register "pcie_port_coalesce" = "true"
  48
  49                         device ref mei1 on end # Management Engine Interface 1
  50                         device ref mei2 off end # Management Engine Interface 2
  51                         device ref me_ide_r off end # Management Engine IDE-R
  52                         device ref me_kt off end # Management Engine KT
  53                         device ref gbe off end # Intel Gigabit Ethernet
  54                         device ref ehci2 on end # USB2 EHCI #2
  55                         device ref hda on end # High Definition Audio
  56                         device ref pcie_rp1 off end # PCIe Port #1 (WLAN remapped)
  57                         device ref pcie_rp2 off end # PCIe Port #2
  58                         device ref pcie_rp3 on end # PCIe Port #3 (WLAN actual)
  59                         device ref pcie_rp4 off end # PCIe Port #4
  60                         device ref pcie_rp5 off end # PCIe Port #5
  61                         device ref pcie_rp6 off end # PCIe Port #6
  62                         device ref pcie_rp7 off end # PCIe Port #7
  63                         device ref pcie_rp8 off end # PCIe Port #8
  64                         device ref ehci1 on end # USB2 EHCI #1
  65                         device ref pci_bridge off end # PCI bridge
  66                         device ref lpc on
  67                                 chip drivers/pc80/tpm
  68                                         device pnp 0c31.0 on end
  69                                 end
  70                                 chip ec/google/chromeec
  71                                         # We only have one init function that
  72                                         # we need to call to initialize the
  73                                         # keyboard part of the EC.
  74                                         device pnp ff.1 on # dummy address
  75                                         end
  76                                 end
  77                         end # LPC bridge
  78                         device ref sata1 on end # SATA Controller 1
  79                         device ref smbus on end # SMBus
  80                         device ref sata2 off end # SATA Controller 2
  81                         device ref thermal on end # Thermal
  82                 end
  83         end
  84 end