mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support
[coreboot.git] / src / mainboard / system76 / adl-p / devicetree.cb
blob8f668bee3318f901b25555f1ecc1ccf24995868a
1 chip soc/intel/alderlake
2 register "common_soc_config" = "{
3 // Touchpad I2C bus
4 .i2c[0] = {
5 .speed = I2C_SPEED_FAST,
6 .rise_time_ns = 80,
7 .fall_time_ns = 110,
8 },
9 }"
11 # Enable Enhanced Intel SpeedStep
12 register "eist_enable" = "1"
14 register "s0ix_enable" = "1"
16 # Enable C6 DRAM
17 register "enable_c6dram" = "1"
19 # Thermal
20 register "tcc_offset" = "8"
22 device cpu_cluster 0 on end
24 device domain 0 on
25 device ref system_agent on end
26 device ref igpu on
27 # DDIA is eDP, DDIB is HDMI
28 register "ddi_portA_config" = "1"
29 register "ddi_ports_config" = "{
30 [DDI_PORT_A] = DDI_ENABLE_HPD,
31 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
34 register "gfx" = "GMA_DEFAULT_PANEL(0)"
35 end
36 device ref tbt_pcie_rp0 on end
37 device ref shared_sram on end
38 device ref cnvi_wifi on
39 register "cnvi_bt_core" = "true"
40 register "cnvi_bt_audio_offload" = "true"
41 chip drivers/wifi/generic
42 register "wake" = "GPE0_PME_B0"
43 device generic 0 on end
44 end
45 end
46 device ref i2c0 on
47 # Touchpad I2C bus
48 register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
49 chip drivers/i2c/hid
50 register "generic.hid" = ""ELAN0412""
51 register "generic.desc" = ""ELAN Touchpad""
52 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
53 register "generic.detect" = "1"
54 register "hid_desc_reg_offset" = "0x01"
55 device i2c 15 on end
56 end
57 chip drivers/i2c/hid
58 register "generic.hid" = ""FTCS1000""
59 register "generic.desc" = ""FocalTech Touchpad""
60 register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
61 register "generic.detect" = "1"
62 register "hid_desc_reg_offset" = "0x01"
63 device i2c 38 on end
64 end
65 end
66 device ref i2c1 on
67 register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
68 end
70 device ref heci1 on end
71 device ref sata on
72 register "sata_salp_support" = "1"
73 register "sata_ports_enable[1]" = "1" # SSD1
74 # FIXME: DevSlp breaks S0ix
75 #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
76 end
77 device ref pch_espi on
78 register "gen1_dec" = "0x00040069" # EC PM channel
79 register "gen2_dec" = "0x00fc0e01" # AP/EC command
80 register "gen3_dec" = "0x00fc0f01" # AP/EC debug
81 chip drivers/pc80/tpm
82 device pnp 0c31.0 on end
83 end
84 end
85 device ref p2sb on end
86 device ref hda on
87 register "pch_hda_idisp_codec_enable" = "1"
88 register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
89 register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
90 end
91 device ref smbus on end
92 device ref fast_spi on end
93 end
94 end