src/soc/amd/common/block/lpc/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/ioapic.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pnp.h>
   8 #include <device/pci_ops.h>
   9 #include <device/pci_def.h>
  10 #include <pc80/mc146818rtc.h>
  11 #include <pc80/isa-dma.h>
  12 #include <pc80/i8254.h>
  13 #include <pc80/i8259.h>
  14 #include <amdblocks/acpi.h>
  15 #include <amdblocks/acpimmio.h>
  16 #include <amdblocks/espi.h>
  17 #include <amdblocks/ioapic.h>
  18 #include <amdblocks/iomap.h>
  19 #include <amdblocks/lpc.h>
  20 #include <soc/iomap.h>
  21 #include <soc/lpc.h>
  22 #include <soc/southbridge.h>
  23
  24 static void setup_serirq(void)
  25 {
  26         u8 byte;
  27
  28         /* Set up SERIRQ, enable continuous mode */
  29         byte = PM_SERIRQ_NUM_BITS_21;
  30         if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
  31                 byte |= PM_SERIRQ_ENABLE;
  32         if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
  33                 byte |= PM_SERIRQ_MODE;
  34
  35         pm_write8(PM_SERIRQ_CONF, byte);
  36 }
  37
  38 static void fch_ioapic_init(void)
  39 {
  40         fch_enable_ioapic_decode();
  41         register_new_ioapic_gsi0(VIO_APIC_VADDR);
  42 }
  43
  44 static void lpc_init(struct device *dev)
  45 {
  46         u8 byte;
  47
  48         /* Initialize isa dma */
  49         isa_dma_init();
  50
  51         /* Enable DMA transaction on the LPC bus */
  52         byte = pci_read_config8(dev, LPC_PCI_CONTROL);
  53         byte |= LEGACY_DMA_EN;
  54         pci_write_config8(dev, LPC_PCI_CONTROL, byte);
  55
  56         /* Disable the timeout mechanism on LPC */
  57         byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
  58         byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;
  59         pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);
  60
  61         /* Disable LPC MSI Capability */
  62         byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);
  63         /* BIT 1 is not defined in public datasheet. */
  64         byte &= ~(1 << 1);
  65
  66         pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);
  67
  68         /*
  69          * Enable hand-instance of the pulse generator and SPI prefetch from
  70          * host (earlier is recommended for boot speed).
  71          */
  72         byte = pci_read_config8(dev, LPC_HOST_CONTROL);
  73         byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;
  74         pci_write_config8(dev, LPC_HOST_CONTROL, byte);
  75
  76         cmos_check_update_date();
  77
  78         /*
  79          * Initialize the real time clock.
  80          * The 0 argument tells cmos_init not to
  81          * update CMOS unless it is invalid.
  82          * 1 tells cmos_init to always initialize the CMOS.
  83          */
  84         cmos_init(0);
  85
  86         /* Initialize i8259 pic */
  87         setup_i8259();
  88
  89         /* Initialize i8254 timers */
  90         setup_i8254();
  91
  92         setup_serirq();
  93
  94         fch_ioapic_init();
  95         fch_configure_hpet();
  96 }
  97
  98 static void lpc_read_resources(struct device *dev)
  99 {
 100         struct resource *res;
 101
 102         /* Get the normal pci resources of this device */
 103         pci_dev_read_resources(dev);
 104
 105         /* Add an extra subtractive resource for both memory and I/O. */
 106         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 107         res->base = 0;
 108         res->size = 0x1000;
 109         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 110                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 111
 112         /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
 113         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 114         res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE;
 115         res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE;
 116         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 117                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 118
 119         /* Add a memory resource for the SPI BAR. */
 120         mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB);
 121
 122         res = new_resource(dev, 3); /* IOAPIC */
 123         res->base = IO_APIC_ADDR;
 124         res->size = 0x00001000;
 125         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 126
 127         compact_resources(dev);
 128 }
 129
 130 static void lpc_set_resources(struct device *dev)
 131 {
 132         struct resource *res;
 133         u32 spi_enable_bits;
 134
 135         /* Special case. The SpiRomEnable and other enables should STAY set. */
 136         res = find_resource(dev, 2);
 137         spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER);
 138         spi_enable_bits &= SPI_BASE_ALIGNMENT - 1;
 139         pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER,
 140                         res->base | spi_enable_bits);
 141
 142         pci_dev_set_resources(dev);
 143 }
 144
 145 static void configure_child_lpc_windows(struct device *dev, struct device *child)
 146 {
 147         struct resource *res;
 148         u32 base, end;
 149         u32 rsize = 0, set = 0, set_x = 0;
 150         int wideio_index;
 151         u32 reg, reg_x;
 152
 153         reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE);
 154         reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
 155
 156         /*
 157          * Be a bit relaxed, tolerate that LPC region might be bigger than
 158          * resource we try to fit, do it like this for all regions < 16 bytes.
 159          * If there is a resource > 16 bytes it must be 512 bytes to be able
 160          * to allocate the fresh LPC window.
 161          *
 162          * AGESA and early initialization can set a wide IO port. This code
 163          * will verify if required region was previously set and will avoid
 164          * setting a new wide IO resource if one is already set.
 165          */
 166
 167         for (res = child->resource_list; res; res = res->next) {
 168                 if (!(res->flags & IORESOURCE_IO))
 169                         continue;
 170                 base = res->base;
 171                 end = resource_end(res);
 172                 printk(BIOS_DEBUG,
 173                         "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n",
 174                         dev_path(child), base, end);
 175                 /* find a resource size */
 176                 switch (base) {
 177                 case 0x60:      /*  KB */
 178                 case 0x64:      /*  MS */
 179                         set |= DECODE_ENABLE_KBC_PORT;
 180                         rsize = 1;
 181                         break;
 182                 case 0x3f8:     /*  COM1 */
 183                         set |= DECODE_ENABLE_SERIAL_PORT0;
 184                         rsize = 8;
 185                         break;
 186                 case 0x2f8:     /*  COM2 */
 187                         set |= DECODE_ENABLE_SERIAL_PORT1;
 188                         rsize = 8;
 189                         break;
 190                 case 0x378:     /*  Parallel 1 */
 191                         set |= DECODE_ENABLE_PARALLEL_PORT0;
 192                         /* enable 0x778 for ECP mode */
 193                         set |= DECODE_ENABLE_PARALLEL_PORT1;
 194                         rsize = 8;
 195                         break;
 196                 case 0x3f0:     /*  FD0 */
 197                         set |= DECODE_ENABLE_FDC_PORT0;
 198                         rsize = 8;
 199                         break;
 200                 case 0x220:     /*  0x220 - 0x227 */
 201                         set |= DECODE_ENABLE_SERIAL_PORT2;
 202                         rsize = 8;
 203                         break;
 204                 case 0x228:     /*  0x228 - 0x22f */
 205                         set |= DECODE_ENABLE_SERIAL_PORT3;
 206                         rsize = 8;
 207                         break;
 208                 case 0x238:     /*  0x238 - 0x23f */
 209                         set |= DECODE_ENABLE_SERIAL_PORT4;
 210                         rsize = 8;
 211                         break;
 212                 case 0x300:     /*  0x300 - 0x301 */
 213                         set |= DECODE_ENABLE_MIDI_PORT0;
 214                         rsize = 2;
 215                         break;
 216                 case 0x400:
 217                         set_x |= DECODE_IO_PORT_ENABLE0;
 218                         rsize = 0x40;
 219                         break;
 220                 case 0x480:
 221                         set_x |= DECODE_IO_PORT_ENABLE1;
 222                         rsize = 0x40;
 223                         break;
 224                 case 0x500:
 225                         set_x |= DECODE_IO_PORT_ENABLE2;
 226                         rsize = 0x40;
 227                         break;
 228                 case 0x580:
 229                         set_x |= DECODE_IO_PORT_ENABLE3;
 230                         rsize = 0x40;
 231                         break;
 232                 case 0x4700:
 233                         set_x |= DECODE_IO_PORT_ENABLE5;
 234                         rsize = 0xc;
 235                         break;
 236                 case 0xfd60:
 237                         set_x |= DECODE_IO_PORT_ENABLE6;
 238                         rsize = 16;
 239                         break;
 240                 default:
 241                         rsize = 0;
 242                         wideio_index = lpc_find_wideio_range(base, res->size);
 243                         if (wideio_index != WIDEIO_RANGE_ERROR) {
 244                                 rsize = lpc_wideio_size(wideio_index);
 245                                 printk(BIOS_DEBUG, "Covered by wideIO");
 246                                 printk(BIOS_DEBUG, " %d\n", wideio_index);
 247                         }
 248                 }
 249                 /* check if region found and matches the enable */
 250                 if (res->size <= rsize) {
 251                         reg |= set;
 252                         reg_x |= set_x;
 253                 /* check if we can fit resource in variable range */
 254                 } else {
 255                         wideio_index = lpc_set_wideio_range(base, res->size);
 256                         if (wideio_index != WIDEIO_RANGE_ERROR) {
 257                                 /* preserve wide IO related bits. */
 258                                 reg_x = pci_read_config32(dev,
 259                                         LPC_IO_OR_MEM_DECODE_ENABLE);
 260                                 printk(BIOS_DEBUG,
 261                                         "Range assigned to wide IO %d\n",
 262                                         wideio_index);
 263                         } else {
 264                                 printk(BIOS_ERR,
 265                                         "cannot fit LPC decode region:");
 266                                 printk(BIOS_ERR,
 267                                         "%s, base = 0x%08x, end = 0x%08x\n",
 268                                         dev_path(child), base, end);
 269                         }
 270                 }
 271         }
 272
 273         pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg);
 274         pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x);
 275 }
 276
 277 static void configure_child_espi_windows(struct device *child)
 278 {
 279         struct resource *res;
 280
 281         for (res = child->resource_list; res; res = res->next) {
 282                 if (res->flags & IORESOURCE_IO)
 283                         espi_open_io_window(res->base, res->size);
 284                 else if (res->flags & IORESOURCE_MEM)
 285                         espi_open_mmio_window(res->base, res->size);
 286         }
 287 }
 288
 289 static void lpc_enable_children_resources(struct device *dev)
 290 {
 291         struct bus *link;
 292         struct device *child;
 293
 294         for (link = dev->link_list; link; link = link->next) {
 295                 for (child = link->children; child; child = child->sibling) {
 296                         if (!child->enabled)
 297                                 continue;
 298                         if (child->path.type != DEVICE_PATH_PNP)
 299                                 continue;
 300                         if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
 301                                 configure_child_espi_windows(child);
 302                         else
 303                                 configure_child_lpc_windows(dev, child);
 304                 }
 305         }
 306 }
 307
 308 static void lpc_enable_resources(struct device *dev)
 309 {
 310         pci_dev_enable_resources(dev);
 311         lpc_enable_children_resources(dev);
 312 }
 313
 314 #if CONFIG(HAVE_ACPI_TABLES)
 315 static const char *lpc_acpi_name(const struct device *dev)
 316 {
 317         return "LPCB";
 318 }
 319 #endif
 320
 321 struct device_operations amd_lpc_ops = {
 322         .read_resources = lpc_read_resources,
 323         .set_resources = lpc_set_resources,
 324         .enable_resources = lpc_enable_resources,
 325 #if CONFIG(HAVE_ACPI_TABLES)
 326         .acpi_name = lpc_acpi_name,
 327         .write_acpi_tables = southbridge_write_acpi_tables,
 328 #endif
 329         .init = lpc_init,
 330         .scan_bus = scan_static_bus,
 331         .ops_pci = &pci_dev_ops_pci,
 332 };