src/soc/amd/glinda/root_complex.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* TODO: Update for Glinda */
   4
   5 #include <acpi/acpigen.h>
   6 #include <amdblocks/acpi.h>
   7 #include <amdblocks/alib.h>
   8 #include <amdblocks/ioapic.h>
   9 #include <amdblocks/memmap.h>
  10 #include <arch/ioapic.h>
  11 #include <cbmem.h>
  12 #include <console/console.h>
  13 #include <cpu/amd/msr.h>
  14 #include <device/device.h>
  15 #include <device/pci.h>
  16 #include <fsp/util.h>
  17 #include <soc/iomap.h>
  18 #include <stdint.h>
  19 #include "chip.h"
  20
  21 #define DPTC_TOTAL_UPDATE_PARAMS        7
  22
  23 struct dptc_input {
  24         uint16_t size;
  25         struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS];
  26 } __packed;
  27
  28 #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow,                    \
  29         _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit)             \
  30         {                                                                       \
  31                 .size = sizeof(struct dptc_input),                              \
  32                 .params = {                                                     \
  33                         {                                                       \
  34                                 .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID,       \
  35                                 .value = _thermctllmit,                         \
  36                         },                                                      \
  37                         {                                                       \
  38                                 .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID,       \
  39                                 .value = _sustained,                            \
  40                         },                                                      \
  41                         {                                                       \
  42                                 .id = ALIB_DPTC_FAST_PPT_LIMIT_ID,              \
  43                                 .value = _fast,                                 \
  44                         },                                                      \
  45                         {                                                       \
  46                                 .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID,              \
  47                                 .value = _slow,                                 \
  48                         },                                                      \
  49                         {                                                       \
  50                                 .id = ALIB_DPTC_VRM_CURRENT_LIMIT_ID,           \
  51                                 .value = _vrmCurrentLimit,                      \
  52                         },                                                      \
  53                         {                                                       \
  54                                 .id = ALIB_DPTC_VRM_MAXIMUM_CURRENT_LIMIT,      \
  55                                 .value = _vrmMaxCurrentLimit,                   \
  56                         },                                                      \
  57                         {                                                       \
  58                                 .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID,       \
  59                                 .value = _vrmSocCurrentLimit,                   \
  60                         },                                                      \
  61                 },                                                              \
  62         }
  63
  64 /*
  65  *
  66  *                     +--------------------------------+
  67  *                     |                                |
  68  *                     |                                |
  69  *                     |                                |
  70  *                     |                                |
  71  *                     |                                |
  72  *                     |                                |
  73  *                     |                                |
  74  *   reserved_dram_end +--------------------------------+
  75  *                     |                                |
  76  *                     |       verstage (if reqd)       |
  77  *                     |          (VERSTAGE_SIZE)       |
  78  *                     +--------------------------------+ VERSTAGE_ADDR
  79  *                     |                                |
  80  *                     |            FSP-M               |
  81  *                     |         (FSP_M_SIZE)           |
  82  *                     +--------------------------------+ FSP_M_ADDR
  83  *                     |           romstage             |
  84  *                     |        (ROMSTAGE_SIZE)         |
  85  *                     +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END
  86  *                     |                                | X86_RESET_VECTOR = BOOTBLOCK_END  - 0x10
  87  *                     |           bootblock            |
  88  *                     |     (C_ENV_BOOTBLOCK_SIZE)     |
  89  *                     +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
  90  *                     |          Unused hole           |
  91  *                     |            (30KiB)             |
  92  *                     +--------------------------------+
  93  *                     |     FMAP cache (FMAP_SIZE)     |
  94  *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
  95  *                     |  Early Timestamp region (512B) |
  96  *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
  97  *                     |      Preram CBMEM console      |
  98  *                     |   (PRERAM_CBMEM_CONSOLE_SIZE)  |
  99  *                     +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
 100  *                     |   PSP shared (vboot workbuf)   |
 101  *                     |      (PSP_SHAREDMEM_SIZE)      |
 102  *                     +--------------------------------+ PSP_SHAREDMEM_BASE
 103  *                     |          APOB (120KiB)         |
 104  *                     +--------------------------------+ PSP_APOB_DRAM_ADDRESS
 105  *                     |        Early BSP stack         |
 106  *                     |   (EARLYRAM_BSP_STACK_SIZE)    |
 107  * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE
 108  *                     |              DRAM              |
 109  *                     +--------------------------------+ 0x100000
 110  *                     |           Option ROM           |
 111  *                     +--------------------------------+ 0xc0000
 112  *                     |           Legacy VGA           |
 113  *                     +--------------------------------+ 0xa0000
 114  *                     |              DRAM              |
 115  *                     +--------------------------------+ 0x0
 116  */
 117 static void read_resources(struct device *dev)
 118 {
 119         uint32_t mem_usable = (uintptr_t)cbmem_top();
 120         unsigned int idx = 0;
 121         const struct hob_header *hob_iterator;
 122         const struct hob_resource *res;
 123         struct resource *gnb_apic;
 124
 125         uintptr_t early_reserved_dram_start, early_reserved_dram_end;
 126         const struct memmap_early_dram *e = memmap_get_early_dram_usage();
 127
 128         early_reserved_dram_start = e->base;
 129         early_reserved_dram_end = e->base + e->size;
 130
 131         /* The root complex has no PCI BARs implemented, so there's no need to call
 132            pci_dev_read_resources for it */
 133
 134         /* 0x0 - 0x9ffff */
 135         ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
 136
 137         /* 0xa0000 - 0xbffff: legacy VGA */
 138         mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
 139
 140         /* 0xc0000 - 0xfffff: Option ROM */
 141         reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 142
 143         /* 1MiB - bottom of DRAM reserved for early coreboot usage */
 144         ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
 145                      (early_reserved_dram_start - (1 * MiB)) / KiB);
 146
 147         /* DRAM reserved for early coreboot usage */
 148         reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
 149                 (early_reserved_dram_end - early_reserved_dram_start) / KiB);
 150
 151         /*
 152          * top of DRAM consumed early - low top usable RAM
 153          * cbmem_top() accounts for low UMA and TSEG if they are used.
 154          */
 155         ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
 156                      (mem_usable - early_reserved_dram_end) / KiB);
 157
 158         mmconf_resource(dev, idx++);
 159
 160         /* GNB IOAPIC resource */
 161         gnb_apic = new_resource(dev, idx++);
 162         gnb_apic->base = GNB_IO_APIC_ADDR;
 163         gnb_apic->size = 0x00001000;
 164         gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 165
 166         if (fsp_hob_iterator_init(&hob_iterator) != CB_SUCCESS) {
 167                 printk(BIOS_ERR, "%s incomplete because no HOB list was found\n",
 168                                 __func__);
 169                 return;
 170         }
 171
 172         while (fsp_hob_iterator_get_next_resource(&hob_iterator, &res) == CB_SUCCESS) {
 173                 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable)
 174                         continue; /* 0 through low usable was set above */
 175                 if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO)
 176                         continue; /* Done separately */
 177
 178                 if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
 179                         ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 180                 else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
 181                         reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 182                 else
 183                         printk(BIOS_ERR, "Failed to set resources for type %d\n",
 184                                         res->type);
 185         }
 186 }
 187
 188 static void root_complex_init(struct device *dev)
 189 {
 190         register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
 191 }
 192
 193 static void acipgen_dptci(void)
 194 {
 195         const struct soc_amd_glinda_config *config = config_of_soc();
 196
 197         /* Normal mode DPTC values. */
 198         struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
 199                 config->sustained_power_limit_mW,
 200                 config->fast_ppt_limit_mW,
 201                 config->slow_ppt_limit_mW,
 202                 config->vrm_current_limit_mA,
 203                 config->vrm_maximum_current_limit_mA,
 204                 config->vrm_soc_current_limit_mA);
 205         acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
 206
 207         /* Low/No Battery */
 208         struct dptc_input no_battery_input = DPTC_INPUTS(
 209                 config->thermctl_limit_degreeC,
 210                 config->sustained_power_limit_mW,
 211                 config->fast_ppt_limit_mW,
 212                 config->slow_ppt_limit_mW,
 213                 config->vrm_current_limit_throttle_mA,
 214                 config->vrm_maximum_current_limit_throttle_mA,
 215                 config->vrm_soc_current_limit_throttle_mA);
 216         acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input,
 217                 sizeof(no_battery_input));
 218 }
 219
 220 static void root_complex_fill_ssdt(const struct device *device)
 221 {
 222         acpi_fill_root_complex_tom(device);
 223         if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 224                 acipgen_dptci();
 225 }
 226
 227 static const char *gnb_acpi_name(const struct device *dev)
 228 {
 229         return "GNB";
 230 }
 231
 232 struct device_operations glinda_root_complex_operations = {
 233         .read_resources         = read_resources,
 234         .set_resources          = noop_set_resources,
 235         .enable_resources       = pci_dev_enable_resources,
 236         .init                   = root_complex_init,
 237         .acpi_name              = gnb_acpi_name,
 238         .acpi_fill_ssdt         = root_complex_fill_ssdt,
 239 };