util/amdfwtool: Add options to separate signed firmwares
[coreboot.git] / util / amdfwtool / amdfwtool.h
blobfd04064f46d4ef9e459b98b140cbb602088954c8
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _AMD_FW_TOOL_H_
4 #define _AMD_FW_TOOL_H_
6 #include <commonlib/bsd/compiler.h>
7 #include <stdint.h>
8 #include <stdbool.h>
10 typedef enum _amd_fw_type {
11 AMD_FW_PSP_PUBKEY = 0,
12 AMD_FW_PSP_BOOTLOADER = 1,
13 AMD_FW_PSP_SMU_FIRMWARE = 8,
14 AMD_FW_PSP_RECOVERY = 3,
15 AMD_FW_PSP_RTM_PUBKEY = 5,
16 AMD_FW_PSP_SECURED_OS = 2,
17 AMD_FW_PSP_NVRAM = 4,
18 AMD_FW_PSP_SECURED_DEBUG = 9,
19 AMD_FW_PSP_TRUSTLETS = 12,
20 AMD_FW_PSP_TRUSTLETKEY = 13,
21 AMD_FW_PSP_SMU_FIRMWARE2 = 18,
22 AMD_PSP_FUSE_CHAIN = 11,
23 AMD_FW_PSP_SMUSCS = 95,
24 AMD_DEBUG_UNLOCK = 0x13,
25 AMD_HW_IPCFG = 0x20,
26 AMD_WRAPPED_IKEK = 0x21,
27 AMD_TOKEN_UNLOCK = 0x22,
28 AMD_SEC_GASKET = 0x24,
29 AMD_MP2_FW = 0x25,
30 AMD_DRIVER_ENTRIES = 0x28,
31 AMD_FW_KVM_IMAGE = 0x29,
32 AMD_S0I3_DRIVER = 0x2d,
33 AMD_ABL0 = 0x30,
34 AMD_ABL1 = 0x31,
35 AMD_ABL2 = 0x32,
36 AMD_ABL3 = 0x33,
37 AMD_ABL4 = 0x34,
38 AMD_ABL5 = 0x35,
39 AMD_ABL6 = 0x36,
40 AMD_ABL7 = 0x37,
41 AMD_FW_PSP_WHITELIST = 0x3a,
42 AMD_VBIOS_BTLOADER = 0x3c,
43 AMD_FW_L2_PTR = 0x40,
44 AMD_FW_USB_PHY = 0x44,
45 AMD_FW_TOS_SEC_POLICY = 0x45,
46 AMD_FW_DRTM_TA = 0x47,
47 AMD_FW_RECOVERYAB_A = 0x48,
48 AMD_FW_RECOVERYAB_B = 0x4A,
49 AMD_FW_BIOS_TABLE = 0x49,
50 AMD_FW_KEYDB_BL = 0x50,
51 AMD_FW_KEYDB_TOS = 0x51,
52 AMD_FW_PSP_VERSTAGE = 0x52,
53 AMD_FW_VERSTAGE_SIG = 0x53,
54 AMD_RPMC_NVRAM = 0x54,
55 AMD_FW_SPL = 0x55,
56 AMD_FW_DMCU_ERAM = 0x58,
57 AMD_FW_DMCU_ISR = 0x59,
58 AMD_FW_MSMU = 0x5a,
59 AMD_FW_SPIROM_CFG = 0x5c,
60 AMD_FW_DMCUB = 0x71,
61 AMD_FW_PSP_BOOTLOADER_AB = 0x73,
62 AMD_TA_IKEK = 0x8d,
63 AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */
64 AMD_FW_GEC,
65 AMD_FW_XHCI,
66 AMD_FW_INVALID, /* Real last one to detect the last entry in table. */
67 AMD_FW_SKIP /* This is for non-applicable options. */
68 } amd_fw_type;
70 typedef enum _amd_bios_type {
71 AMD_BIOS_RTM_PUBKEY = 0x05,
72 AMD_BIOS_SIG = 0x07,
73 AMD_BIOS_APCB = 0x60,
74 AMD_BIOS_APOB = 0x61,
75 AMD_BIOS_BIN = 0x62,
76 AMD_BIOS_APOB_NV = 0x63,
77 AMD_BIOS_PMUI = 0x64,
78 AMD_BIOS_PMUD = 0x65,
79 AMD_BIOS_UCODE = 0x66,
80 AMD_BIOS_APCB_BK = 0x68,
81 AMD_BIOS_MP2_CFG = 0x6a,
82 AMD_BIOS_PSP_SHARED_MEM = 0x6b,
83 AMD_BIOS_L2_PTR = 0x70,
84 AMD_BIOS_INVALID,
85 AMD_BIOS_SKIP
86 } amd_bios_type;
88 typedef enum _amd_addr_mode {
89 AMD_ADDR_PHYSICAL = 0, /* Physical address */
90 AMD_ADDR_REL_BIOS, /* Relative to beginning of image */
91 AMD_ADDR_REL_TAB, /* Relative to table */
92 AMD_ADDR_REL_SLOT, /* Relative to slot */
93 } amd_addr_mode;
95 struct second_gen_efs { /* todo: expand for Server products */
96 int gen:1; /* Client products only use bit 0 */
97 int reserved:31;
98 } __attribute__((packed));
100 #define EFS_SECOND_GEN 0
101 #define EFS_BEFORE_SECOND_GEN 1
103 typedef struct _embedded_firmware {
104 uint32_t signature; /* 0x55aa55aa */
105 uint32_t imc_entry;
106 uint32_t gec_entry;
107 uint32_t xhci_entry;
108 uint32_t psp_directory;
109 union {
110 uint32_t new_psp_directory;
111 uint32_t combo_psp_directory;
113 uint32_t bios0_entry; /* todo: add way to select correct entry */
114 uint32_t bios1_entry;
115 uint32_t bios2_entry;
116 struct second_gen_efs efs_gen;
117 uint32_t bios3_entry;
118 uint32_t reserved_2Ch;
119 uint32_t promontory_fw_ptr;
120 uint32_t lp_promontory_fw_ptr;
121 uint32_t reserved_38h;
122 uint32_t reserved_3Ch;
123 uint8_t spi_readmode_f15_mod_60_6f;
124 uint8_t fast_speed_new_f15_mod_60_6f;
125 uint8_t reserved_42h;
126 uint8_t spi_readmode_f17_mod_00_2f;
127 uint8_t spi_fastspeed_f17_mod_00_2f;
128 uint8_t qpr_dummy_cycle_f17_mod_00_2f;
129 uint8_t reserved_46h;
130 uint8_t spi_readmode_f17_mod_30_3f;
131 uint8_t spi_fastspeed_f17_mod_30_3f;
132 uint8_t micron_detect_f17_mod_30_3f;
133 uint8_t reserved_4Ah;
134 uint8_t reserved_4Bh;
135 uint32_t reserved_4Ch;
136 } __attribute__((packed, aligned(16))) embedded_firmware;
138 typedef struct _psp_directory_header {
139 uint32_t cookie;
140 uint32_t checksum;
141 uint32_t num_entries;
142 union {
143 uint32_t additional_info;
144 struct {
145 uint32_t dir_size:10;
146 uint32_t spi_block_size:4;
147 uint32_t base_addr:15;
148 uint32_t address_mode:2;
149 uint32_t not_used:1;
150 } __attribute__((packed)) additional_info_fields;
152 } __attribute__((packed, aligned(16))) psp_directory_header;
154 typedef struct _psp_directory_entry {
155 uint8_t type;
156 uint8_t subprog;
157 uint16_t rsvd;
158 uint32_t size;
159 uint64_t addr:62; /* or a value in some cases */
160 uint64_t address_mode:2;
161 } __attribute__((packed)) psp_directory_entry;
163 typedef struct _psp_directory_table {
164 psp_directory_header header;
165 psp_directory_entry entries[];
166 } __attribute__((packed, aligned(16))) psp_directory_table;
168 #define MAX_PSP_ENTRIES 0x2f
170 typedef struct _psp_combo_header {
171 uint32_t cookie;
172 uint32_t checksum;
173 uint32_t num_entries;
174 uint32_t lookup;
175 uint64_t reserved[2];
176 } __attribute__((packed, aligned(16))) psp_combo_header;
178 typedef struct _psp_combo_entry {
179 uint32_t id_sel;
180 uint32_t id;
181 uint64_t lvl2_addr;
182 } __attribute__((packed)) psp_combo_entry;
184 typedef struct _psp_combo_directory {
185 psp_combo_header header;
186 psp_combo_entry entries[];
187 } __attribute__((packed, aligned(16))) psp_combo_directory;
189 #define MAX_COMBO_ENTRIES 1
191 typedef struct _bios_directory_hdr {
192 uint32_t cookie;
193 uint32_t checksum;
194 uint32_t num_entries;
195 union {
196 uint32_t additional_info;
197 struct {
198 uint32_t dir_size:10;
199 uint32_t spi_block_size:4;
200 uint32_t base_addr:15;
201 uint32_t address_mode:2;
202 uint32_t not_used:1;
203 } __attribute__((packed)) additional_info_fields;
205 } __attribute__((packed, aligned(16))) bios_directory_hdr;
207 typedef struct _bios_directory_entry {
208 uint8_t type;
209 uint8_t region_type;
210 int reset:1;
211 int copy:1;
212 int ro:1;
213 int compressed:1;
214 int inst:4;
215 uint8_t subprog; /* b[7:3] reserved */
216 uint32_t size;
217 uint64_t source:62;
218 uint64_t address_mode:2;
219 uint64_t dest;
220 } __attribute__((packed)) bios_directory_entry;
222 typedef struct _bios_directory_table {
223 bios_directory_hdr header;
224 bios_directory_entry entries[];
225 } bios_directory_table;
227 #define MAX_BIOS_ENTRIES 0x2f
229 #define BDT_LVL1 (1 << 0)
230 #define BDT_LVL2 (1 << 1)
231 #define BDT_LVL1_AB (1 << 2)
232 #define BDT_LVL2_AB (1 << 3)
233 #define BDT_BOTH (BDT_LVL1 | BDT_LVL2)
234 #define BDT_BOTH_AB (BDT_LVL1_AB | BDT_LVL2_AB)
235 typedef struct _amd_bios_entry {
236 amd_bios_type type;
237 char *filename;
238 int subpr;
239 int region_type;
240 int reset;
241 int copy;
242 int ro;
243 int zlib;
244 int inst;
245 uint64_t src;
246 uint64_t dest;
247 size_t size;
248 int level;
249 } amd_bios_entry;
251 typedef struct _ish_directory_table {
252 uint32_t checksum;
253 uint32_t boot_priority;
254 uint32_t update_retry_count;
255 uint8_t glitch_retry_count;
256 uint8_t glitch_higherbits_reserved[3];
257 uint32_t pl2_location;
258 uint32_t psp_id;
259 uint32_t slot_max_size;
260 uint32_t reserved;
261 } __attribute__((packed)) ish_directory_table;
263 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa
264 #define PSP_COOKIE 0x50535024 /* 'PSP$' */
265 #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */
266 #define PSP2_COOKIE 0x50535032 /* 'PSP2' */
267 #define BHD_COOKIE 0x44484224 /* 'DHB$ */
268 #define BHDL2_COOKIE 0x324c4224 /* '2LB$ */
270 #define PSP_LVL1 (1 << 0)
271 #define PSP_LVL2 (1 << 1)
272 #define PSP_LVL1_AB (1 << 2)
273 #define PSP_LVL2_AB (1 << 3)
274 #define PSP_BOTH (PSP_LVL1 | PSP_LVL2)
275 #define PSP_BOTH_AB (PSP_LVL1_AB | PSP_LVL2_AB)
276 typedef struct _amd_fw_entry {
277 amd_fw_type type;
278 /* Mendocino and later SoCs use fw_id instead of fw_type. fw_type is still around
279 for backwards compatibility. fw_id can be populated from the PSP binary file. */
280 uint16_t fw_id;
281 char *filename;
282 uint8_t subprog;
283 uint64_t dest;
284 size_t size;
285 int level;
286 uint64_t other;
287 /* If the binary is signed and the tool is invoked to keep the signed binaries separate,
288 then this field is populated with the offset of the concerned PSP binary (relative to
289 BIOS or PSP Directory table). */
290 uint64_t addr_signed;
291 uint32_t file_size;
292 /* Some files that don't have amd_fw_header have to be skipped from hashing. These files
293 include but not limited to: *iKek*, *.tkn, *.stkn */
294 bool skip_hashing;
295 } amd_fw_entry;
297 /* Most PSP binaries, if not all, have the following header format. */
298 struct amd_fw_header {
299 uint8_t reserved_0[20];
300 uint32_t fw_size_signed;
301 uint8_t reserved_18[24];
302 /* 1 if the image is signed, 0 otherwise */
303 uint32_t sig_opt;
304 uint32_t sig_id;
305 uint8_t sig_param[16];
306 uint32_t comp_opt;
307 uint8_t reserved_4c[4];
308 uint32_t uncomp_size;
309 uint32_t comp_size;
310 /* Starting MDN fw_id is populated instead of fw_type. */
311 uint16_t fw_id;
312 uint8_t reserved_5a[18];
313 uint32_t size_total;
314 uint8_t reserved_70[12];
315 /* Starting MDN fw_id is populated instead of fw_type. fw_type will still be around
316 for backwards compatibility. */
317 uint8_t fw_type;
318 uint8_t fw_subtype;
319 uint8_t fw_subprog;
320 uint8_t reserved_7f;
321 uint8_t reserved_80[128];
322 } __packed;
324 typedef struct _amd_cb_config {
325 bool have_whitelist;
326 bool unlock_secure;
327 bool use_secureos;
328 bool load_mp2_fw;
329 bool multi_level;
330 bool s0i3;
331 bool second_gen;
332 bool have_mb_spl;
333 bool recovery_ab;
334 bool recovery_ab_single_copy;
335 bool need_ish;
336 bool use_combo;
337 } amd_cb_config;
339 void register_fw_fuse(char *str);
340 uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps);
342 #define OK 0
344 #define LINE_EOF (1)
345 #define LINE_TOO_LONG (2)
347 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
349 #endif /* _AMD_FW_TOOL_H_ */