src/soc/intel/alderlake/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
   3 subdirs-y += romstage
   4 subdirs-y += ../../../cpu/intel/microcode
   5 subdirs-y += ../../../cpu/intel/turbo
   6
   7 # all (bootblock, verstage, romstage, postcar, ramstage)
   8 all-y += gspi.c
   9 all-y += i2c.c
  10 all-y += pmutil.c
  11 all-y += spi.c
  12 all-y += uart.c
  13
  14 bootblock-y += bootblock/bootblock.c
  15 bootblock-y += bootblock/pch.c
  16 bootblock-y += bootblock/report_platform.c
  17 bootblock-y += espi.c
  18 bootblock-y += p2sb.c
  19 bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
  20
  21 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c
  22 romstage-y += espi.c
  23 romstage-y += meminit.c
  24 romstage-y += pcie_rp.c
  25 romstage-y += reset.c
  26
  27 ramstage-y += acpi.c
  28 ramstage-y += chip.c
  29 ramstage-y += cpu.c
  30 ramstage-y += elog.c
  31 ramstage-y += espi.c
  32 ramstage-y += finalize.c
  33 ramstage-y += fsp_params.c
  34 ramstage-y += graphics.c
  35 ramstage-y += hsphy.c
  36 ramstage-y += lockdown.c
  37 ramstage-y += p2sb.c
  38 ramstage-y += pcie_rp.c
  39 ramstage-y += pmc.c
  40 ramstage-y += reset.c
  41 ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
  42 ramstage-y += soundwire.c
  43 ramstage-y += systemagent.c
  44 ramstage-y += tcss.c
  45 ramstage-y += vr_config.c
  46 ramstage-y += xhci.c
  47 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
  48
  49 smm-y += elog.c
  50 smm-y += p2sb.c
  51 smm-y += pmutil.c
  52 smm-y += smihandler.c
  53 smm-y += uart.c
  54 smm-y += xhci.c
  55
  56 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
  57 bootblock-y += gpio_pch_s.c
  58 romstage-y += gpio_pch_s.c
  59 ramstage-y += gpio_pch_s.c
  60 smm-y += gpio_pch_s.c
  61 verstage-y += gpio_pch_s.c
  62 else
  63 bootblock-y += gpio.c
  64 romstage-y += gpio.c
  65 ramstage-y += gpio.c
  66 smm-y += gpio.c
  67 verstage-y += gpio.c
  68 endif
  69
  70 CPPFLAGS_common += -I$(src)/soc/intel/alderlake
  71 CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
  72
  73 # Include the missing MemInfoHob.h from vendorcode
  74 ifeq ($(CONFIG_SOC_INTEL_RAPTORLAKE_PCH_S)$(CONFIG_FSP_TYPE_IOT),yy)
  75 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s
  76 endif
  77
  78 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
  79 # 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
  80 # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
  81 # 06-b7-00 are RPL-S Engineering Samples
  82 # ADL-S/HX C0/H0 and RPL-S C0/H0
  83 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
  84 # RPL-S/HX B0
  85 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01
  86 else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
  87 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00
  88 else
  89 # 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples
  90 # Missing 06-9a-02 ADL-P K0
  91 # ADL-P L0, ADL-P R0 and ADL-M R0
  92 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04
  93 # RPL-P/H J0, RPL-U Q0
  94 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ba-02
  95 endif
  96
  97 ifeq ($(CONFIG_STITCH_ME_BIN),y)
  98
  99 $(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))
 100 $(eval $(call cse_add_dummy_to_bp1_bp2,IFPP))
 101 $(eval $(call cse_add_dummy_to_bp1_bp2,SBDT))
 102 $(eval $(call cse_add_decomp_to_bp1_bp2,RBEP))
 103 $(eval $(call cse_add_dummy_to_bp1_bp2,UFSP))
 104 $(eval $(call cse_add_dummy_to_bp1_bp2,UFSG))
 105 $(eval $(call cse_add_input_to_bp1_bp2,OEMP))
 106 $(eval $(call cse_add_input_to_bp1_bp2,PMCP))
 107 $(eval $(call cse_add_decomp,bp1,MFTP))
 108 $(eval $(call cse_add_decomp,bp2,FTPR))
 109 $(eval $(call cse_add_input_to_bp1_bp2,IOMP))
 110 $(eval $(call cse_add_input_to_bp1_bp2,NPHY))
 111 $(eval $(call cse_add_input_to_bp1_bp2,TBTP))
 112 $(eval $(call cse_add_input_to_bp1_bp2,PCHC))
 113 $(eval $(call cse_add_decomp,bp2,NFTP))
 114 $(eval $(call cse_add_dummy,bp2,ISHP))
 115 $(eval $(call cse_add_input,bp2,IUNP))
 116
 117 endif
 118
 119 ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
 120 ifneq ($(call strip_quotes,$(CONFIG_HSPHY_FW_FILE)),)
 121
 122 # Create the target HSPHY file that will be put into flashmap region.
 123 # First goes the HSPHY size, then hash algorithm (3 - SHA384, default for now),
 124 # the hash digest, padding to max digest size (SHA512 - 64 bytes) and at last the
 125 # HSPHY firmware itself
 126 $(obj)/hsphy_fw.bin: $(call strip_quotes,$(top)/$(CONFIG_HSPHY_FW_FILE))
 127         printf "    HSPHY      $(obj)/hsphy_fw.bin\n"
 128         $(shell wc -c $< | awk '{print $$1}' | tr -d '\n' | xargs -0 printf '%08X' | \
 129                          tac -rs .. | xxd -r -p > $@)
 130         $(shell printf '%02X' 3 | xxd -r -p >> $@)
 131         $(shell sha384sum $< | awk '{print $$1}' | tac -rs .. | xxd -r -p >> $@)
 132         $(shell dd if=/dev/zero bs=1 count=16 2> /dev/null >> $@)
 133         $(shell cat $< >> $@)
 134
 135 add_hsphy_firmware: $(obj)/hsphy_fw.bin $(obj)/fmap.fmap $(obj)/coreboot.pre $(CBFSTOOL)
 136         $(CBFSTOOL) $(obj)/coreboot.pre write -u -r HSPHY_FW -f $(obj)/hsphy_fw.bin
 137
 138 $(call add_intermediate, add_hsphy_firmware)
 139
 140 endif
 141 endif
 142
 143 endif