src/soc/intel/alderlake/gpio_pch_s.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pmc.h>
   7
   8 #define DEFAULT_VW_BASE         0x10
   9
  10 /*
  11  * This file is created based on Intel Alder Lake Processor PCH-S Datasheet
  12  */
  13
  14 static const struct reset_mapping rst_map_gpp[] = {
  15         { .logical = PAD_RESET(RSMRST), .chipset = 0U << 30 },
  16         { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
  17         { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
  18 };
  19 static const struct reset_mapping rst_map_gpd[] = {
  20         { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
  21         { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
  22         { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
  23         { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 },
  24 };
  25
  26 /*
  27  * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad
  28  * group, regardless of whether or not there is a physical pad for each
  29  * exposed GPIO number.
  30  *
  31  * This results in the OS having a sparse GPIO map, and devices that need
  32  * to export an ACPI GPIO must use the OS expected number.
  33  *
  34  * Not all pins are usable as GPIO and those groups do not have a pad base.
  35  */
  36 static const struct pad_group adl_community0_groups[] = {
  37         INTEL_GPP_BASE(GPP_I0, GPP_I0, GPP_GSPI1_CLK_LOOPBK, 0),        /* GPP_I */
  38         INTEL_GPP_BASE(GPP_I0, GPP_R0, GPP_GSPI2_CLK_LOOPBK, 32),       /* GPP_R */
  39         INTEL_GPP_BASE(GPP_I0, GPP_J0, GPP_J11, 64),                    /* GPP_J */
  40         INTEL_GPP_BASE(GPP_I0, VGPIO_0, VGPIO_37, 96),                  /* vGPIO */
  41         INTEL_GPP_BASE(GPP_I0, VGPIO_USB_0, VGPIO_USB_11, 128),         /* vGPIO_0 */
  42 };
  43
  44 static const struct vw_entries adl_community0_vw[] = {
  45         {GPP_I0, GPP_I14},
  46         {GPP_R0, GPP_R19},
  47         {GPP_J0, GPP_J9},
  48 };
  49
  50 static const struct pad_group adl_community1_groups[] = {
  51         INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B23, 160),           /* GPP_B */
  52         INTEL_GPP_BASE(GPP_B0, GPP_G0, GPP_G7, 192),            /* GPP_G */
  53         INTEL_GPP_BASE(GPP_B0, GPP_H0, GPP_H23, 224),           /* GPP_H */
  54 };
  55
  56 static const struct vw_entries adl_community1_vw[] = {
  57         {GPP_B0, GPP_B23},
  58         {GPP_G0, GPP_G7},
  59         {GPP_H0, GPP_H23},
  60 };
  61
  62 /* This community is not visible to the OS */
  63 static const struct pad_group adl_community2_groups[] = {
  64         INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB),                 /* GPD */
  65 };
  66
  67 static const struct pad_group adl_community3_groups[] = {
  68         INTEL_GPP(GPP_SPI0_IO_2, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK),           /* SPI0 */
  69         INTEL_GPP_BASE(GPP_SPI0_IO_2, GPP_A0, GPP_ESPI_CLK_LOOPBK, 256),        /* GPP_A */
  70         INTEL_GPP_BASE(GPP_SPI0_IO_2, GPP_C0, GPP_C23, 288),                    /* GPP_C */
  71         INTEL_GPP(GPP_SPI0_IO_2, VGPIO_PCIE_0, VGPIO_PCIE_83),                  /* vGPIO_3 */
  72 };
  73
  74 static const struct vw_entries adl_community3_vw[] = {
  75         {GPP_A0, GPP_A14},
  76         {GPP_C0, GPP_C23},
  77 };
  78
  79 static const struct pad_group adl_community4_groups[] = {
  80         INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 320),                            /* GPP_S */
  81         INTEL_GPP_BASE(GPP_S0, GPP_E0, GPP_SPI1_THC0_CLK_LOOPBK, 352),          /* GPP_E */
  82         INTEL_GPP_BASE(GPP_S0, GPP_K0, GPP_MLK_RSTB, 384),                      /* GPP_K */
  83         INTEL_GPP_BASE(GPP_S0, GPP_F0, GPP_F23, 416),                           /* GPP_F */
  84 };
  85
  86 static const struct vw_entries adl_community4_vw[] = {
  87         {GPP_E0, GPP_E21},
  88         {GPP_K0, GPP_K11},
  89         {GPP_F0, GPP_F23},
  90 };
  91
  92 static const struct pad_group adl_community5_groups[] = {
  93         INTEL_GPP_BASE(GPP_D0, GPP_D0, GPP_GSPI3_THC1_CLK_LOOPBK, 448),         /* GPP_D */
  94         INTEL_GPP(GPP_D0, GPP_JTAG_TDO, GPP_CPU_TRSTB),                         /* JTAG */
  95         INTEL_GPP(GPP_D0, GPP_HDACPU_SDI, GPP_C10_WAKE),                        /* CPU */
  96 };
  97
  98 static const struct pad_community adl_communities[] = {
  99         [COMM_0] = { /* GPP I, R, J, vGPIO. vGPIO_0 */
 100                 .port = PID_GPIOCOM0,
 101                 .cpu_port = PID_CPU_GPIOCOM0,
 102                 .first_pad = GPIO_COM0_START,
 103                 .last_pad = GPIO_COM0_END,
 104                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
 105                 .pad_cfg_base = PAD_CFG_BASE,
 106                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 107                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 108                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 109                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 110                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 111                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 112                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 113                 .name = "GPP_IRJ",
 114                 .acpi_path = "\\_SB.PCI0.GPIO",
 115                 .reset_map = rst_map_gpp,
 116                 .num_reset_vals = ARRAY_SIZE(rst_map_gpp),
 117                 .groups = adl_community0_groups,
 118                 .num_groups = ARRAY_SIZE(adl_community0_groups),
 119                 .vw_base = DEFAULT_VW_BASE,
 120                 .vw_entries = adl_community0_vw,
 121                 .num_vw_entries = ARRAY_SIZE(adl_community0_vw),
 122         },
 123         [COMM_1] = { /* GPP B, G, H */
 124                 .port = PID_GPIOCOM1,
 125                 .cpu_port = PID_CPU_GPIOCOM1,
 126                 .first_pad = GPIO_COM1_START,
 127                 .last_pad = GPIO_COM1_END,
 128                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 129                 .pad_cfg_base = PAD_CFG_BASE,
 130                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 131                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 132                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 133                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 134                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 135                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 136                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 137                 .name = "GPP_BGH",
 138                 .acpi_path = "\\_SB.PCI0.GPIO",
 139                 .reset_map = rst_map_gpp,
 140                 .num_reset_vals = ARRAY_SIZE(rst_map_gpp),
 141                 .groups = adl_community1_groups,
 142                 .num_groups = ARRAY_SIZE(adl_community1_groups),
 143                 .vw_base = DEFAULT_VW_BASE,
 144                 .vw_entries = adl_community1_vw,
 145                 .num_vw_entries = ARRAY_SIZE(adl_community1_vw),
 146         },
 147         [COMM_2] = { /* GPD */
 148                 .port = PID_GPIOCOM2,
 149                 .first_pad = GPIO_COM2_START,
 150                 .last_pad = GPIO_COM2_END,
 151                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 152                 .pad_cfg_base = PAD_CFG_BASE,
 153                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 154                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 155                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 156                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 157                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 158                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 159                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 160                 .name = "GPD",
 161                 .acpi_path = "\\_SB.PCI0.GPIO",
 162                 .reset_map = rst_map_gpd,
 163                 .num_reset_vals = ARRAY_SIZE(rst_map_gpd),
 164                 .groups = adl_community2_groups,
 165                 .num_groups = ARRAY_SIZE(adl_community2_groups),
 166         },
 167         [COMM_3] = { /* SPI0, GPP A, C */
 168                 .port = PID_GPIOCOM3,
 169                 .cpu_port = PID_CPU_GPIOCOM3,
 170                 .first_pad = GPIO_COM3_START,
 171                 .last_pad = GPIO_COM3_END,
 172                 .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 173                 .pad_cfg_base = PAD_CFG_BASE,
 174                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 175                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 176                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 177                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 178                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 179                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 180                 .name = "GPP_AC",
 181                 .acpi_path = "\\_SB.PCI0.GPIO",
 182                 .reset_map = rst_map_gpp,
 183                 .num_reset_vals = ARRAY_SIZE(rst_map_gpp),
 184                 .groups = adl_community3_groups,
 185                 .num_groups = ARRAY_SIZE(adl_community3_groups),
 186                 .vw_base = DEFAULT_VW_BASE,
 187                 .vw_entries = adl_community3_vw,
 188                 .num_vw_entries = ARRAY_SIZE(adl_community3_vw),
 189         },
 190         [COMM_4] = { /* GPP S, E, K, F */
 191                 .port = PID_GPIOCOM4,
 192                 .cpu_port = PID_CPU_GPIOCOM4,
 193                 .first_pad = GPIO_COM4_START,
 194                 .last_pad = GPIO_COM4_END,
 195                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 196                 .pad_cfg_base = PAD_CFG_BASE,
 197                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 198                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 199                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 200                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 201                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 202                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 203                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 204                 .name = "GPP_SEKF",
 205                 .acpi_path = "\\_SB.PCI0.GPIO",
 206                 .reset_map = rst_map_gpp,
 207                 .num_reset_vals = ARRAY_SIZE(rst_map_gpp),
 208                 .groups = adl_community4_groups,
 209                 .num_groups = ARRAY_SIZE(adl_community4_groups),
 210                 .vw_base = DEFAULT_VW_BASE,
 211                 .vw_entries = adl_community4_vw,
 212                 .num_vw_entries = ARRAY_SIZE(adl_community4_vw),
 213         },
 214         [COMM_5] = { /* GPP D, JTAG, CPU */
 215                 .port = PID_GPIOCOM5,
 216                 .cpu_port = PID_CPU_GPIOCOM5,
 217                 .first_pad = GPIO_COM5_START,
 218                 .last_pad = GPIO_COM5_END,
 219                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 220                 .pad_cfg_base = PAD_CFG_BASE,
 221                 .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
 222                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 223                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 224                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 225                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 226                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 227                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 228                 .name = "GPP_D",
 229                 .acpi_path = "\\_SB.PCI0.GPIO",
 230                 .reset_map = rst_map_gpp,
 231                 .num_reset_vals = ARRAY_SIZE(rst_map_gpp),
 232                 .groups = adl_community5_groups,
 233                 .num_groups = ARRAY_SIZE(adl_community5_groups),
 234         }
 235 };
 236
 237 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 238 {
 239         *num_communities = ARRAY_SIZE(adl_communities);
 240         return adl_communities;
 241 }
 242
 243 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 244 {
 245         static const struct pmc_to_gpio_route routes[] = {
 246                 {  PMC_GPP_I,    GPP_I },
 247                 {  PMC_GPP_R,    GPP_R },
 248                 {  PMC_GPP_J,    GPP_J },
 249                 {  PMC_GPD,      GPD   },
 250                 {  PMC_GPP_D,    GPP_D },
 251                 {  PMC_GPP_S,    GPP_S },
 252                 {  PMC_GPP_E,    GPP_E },
 253                 {  PMC_GPP_K,    GPP_K },
 254                 {  PMC_GPP_F,    GPP_F },
 255                 {  PMC_GPP_A,    GPP_A },
 256                 {  PMC_GPP_C,    GPP_C },
 257                 {  PMC_GPP_B,    GPP_B },
 258                 {  PMC_GPP_G,    GPP_G },
 259                 {  PMC_GPP_H,    GPP_H },
 260         };
 261         *num = ARRAY_SIZE(routes);
 262         return routes;
 263 };