src/soc/intel/alderlake/lockdown.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor PCH Datasheet
   5  * Document number: 621483
   6  * Chapter number: 4
   7  */
   8
   9 #include <device/mmio.h>
  10 #include <intelblocks/cfg.h>
  11 #include <intelblocks/pcr.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelpch/lockdown.h>
  14 #include <soc/pcr_ids.h>
  15 #include <soc/pm.h>
  16 #include <stdint.h>
  17
  18 /* PCR PSTH Control Register */
  19 #define PCR_PSTH_CTRLREG                0x1d00
  20 #define   PSTH_CTRLREG_IOSFPTCGE        (1 << 2)
  21
  22 static void pmc_lockdown_cfg(int chipset_lockdown)
  23 {
  24         uint8_t *pmcbase = pmc_mmio_regs();
  25
  26         /* PMSYNC */
  27         setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK);
  28         /* Lock down ABASE and sleep stretching policy */
  29         setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
  30
  31         if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
  32                 setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
  33
  34         if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
  35                 setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
  36                 setbits32(pmcbase + SSML, SSML_SSL_EN);
  37                 setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK |
  38                                          PM_CFG_XRAM_READ_DISABLE);
  39         }
  40
  41         /* Send PMC IPC to inform about both BIOS Reset and PCI enumeration done */
  42         pmc_send_bios_reset_pci_enum_done();
  43 }
  44
  45 static void pch_lockdown_cfg(void)
  46 {
  47         if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
  48                 return;
  49
  50         /* Enable IOSF Primary Trunk Clock Gating */
  51         pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
  52 }
  53
  54 void soc_lockdown_config(int chipset_lockdown)
  55 {
  56         /* PMC lock down configuration */
  57         pmc_lockdown_cfg(chipset_lockdown);
  58         /* PCH lock down configuration */
  59         pch_lockdown_cfg();
  60 }