src/soc/intel/apollolake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <console/console.h>
   8 #include <device/device.h>
   9 #include <device/mmio.h>
  10 #include <arch/smp/mpspec.h>
  11 #include <assert.h>
  12 #include <device/pci_ops.h>
  13 #include <gpio.h>
  14 #include <intelblocks/acpi.h>
  15 #include <intelblocks/pmclib.h>
  16 #include <intelblocks/p2sb.h>
  17 #include <soc/iomap.h>
  18 #include <soc/pm.h>
  19 #include <soc/nvs.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/systemagent.h>
  22
  23 #include "chip.h"
  24
  25 #define CSTATE_RES(address_space, width, offset, address)               \
  26         {                                                               \
  27         .space_id = address_space,                                      \
  28         .bit_width = width,                                             \
  29         .bit_offset = offset,                                           \
  30         .addrl = address,                                               \
  31         }
  32
  33 static const acpi_cstate_t cstate_map[] = {
  34         {
  35                 /* C1 */
  36                 .ctype = 1,             /* ACPI C1 */
  37                 .latency = 1,
  38                 .power = 1000,
  39                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0),
  40         },
  41         {
  42                 .ctype = 2,             /* ACPI C2 */
  43                 .latency = 50,
  44                 .power = 10,
  45                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415),
  46         },
  47         {
  48                 .ctype = 3,             /* ACPI C3 */
  49                 .latency = 150,
  50                 .power = 10,
  51                 .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419),
  52         }
  53 };
  54
  55 uint32_t soc_read_sci_irq_select(void)
  56 {
  57         return read32p(soc_read_pmc_base() + IRQ_REG);
  58 }
  59
  60 void soc_write_sci_irq_select(uint32_t scis)
  61 {
  62         write32p(soc_read_pmc_base() + IRQ_REG, scis);
  63 }
  64
  65 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
  66 {
  67         *entries = ARRAY_SIZE(cstate_map);
  68         return cstate_map;
  69 }
  70
  71 void soc_fill_gnvs(struct global_nvs *gnvs)
  72 {
  73         struct soc_intel_apollolake_config *cfg;
  74         cfg = config_of_soc();
  75
  76         /* Enable DPTF based on mainboard configuration */
  77         gnvs->dpte = cfg->dptf_enable;
  78
  79         /* Assign address of PERST_0 if GPIO is defined in devicetree */
  80         if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
  81                 gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
  82
  83         /* Get sdcard cd GPIO portid if GPIO is defined in devicetree.
  84          * Get offset of sdcard cd pin.
  85          */
  86         if (cfg->sdcard_cd_gpio) {
  87                 gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio);
  88                 gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
  89         }
  90 }
  91
  92 int soc_madt_sci_irq_polarity(int sci)
  93 {
  94         return MP_IRQ_POLARITY_LOW;
  95 }
  96
  97 void soc_fill_fadt(acpi_fadt_t *fadt)
  98 {
  99         const struct soc_intel_apollolake_config *cfg;
 100         cfg = config_of_soc();
 101
 102         fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
 103
 104         fadt->pm_tmr_len = 4;
 105
 106         fill_fadt_extended_pm_io(fadt);
 107
 108         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
 109
 110         if (cfg->lpss_s0ix_enable)
 111                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 112 }
 113
 114 static unsigned long soc_fill_dmar(unsigned long current)
 115 {
 116         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 117         uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
 118         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 119         bool defvten = MCHBAR32(DEFVTBAR) & VTBAR_ENABLED;
 120         unsigned long tmp;
 121
 122         /* IGD has to be enabled, GFXVTBAR set and enabled. */
 123         const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
 124
 125         /* First, add DRHD entries */
 126         if (emit_igd) {
 127                 tmp = current;
 128
 129                 current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
 130                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 131                 acpi_dmar_drhd_fixup(tmp, current);
 132         }
 133
 134         /* DEFVTBAR has to be set and enabled. */
 135         if (defvtbar && defvten) {
 136                 tmp = current;
 137                 union p2sb_bdf ibdf = p2sb_get_ioapic_bdf();
 138                 union p2sb_bdf hbdf = p2sb_get_hpet_bdf();
 139                 p2sb_hide();
 140
 141                 current += acpi_create_dmar_drhd_4k(current,
 142                                 DRHD_INCLUDE_PCI_ALL, 0, defvtbar);
 143                 current += acpi_create_dmar_ds_ioapic_from_hw(current,
 144                                 IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn);
 145                 current += acpi_create_dmar_ds_msi_hpet(current,
 146                                 0, hbdf.bus, hbdf.dev, hbdf.fn);
 147                 acpi_dmar_drhd_fixup(tmp, current);
 148         }
 149
 150         /* Then, add RMRR entries after all DRHD entries */
 151         if (emit_igd) {
 152                 tmp = current;
 153                 current += acpi_create_dmar_rmrr(current, 0,
 154                                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 155                 current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
 156                 acpi_dmar_rmrr_fixup(tmp, current);
 157         }
 158
 159         return current;
 160 }
 161
 162 unsigned long sa_write_acpi_tables(const struct device *const dev,
 163                                      unsigned long current,
 164                                      struct acpi_rsdp *const rsdp)
 165 {
 166         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 167
 168         /* Create DMAR table only if virtualization is enabled. Due to some
 169          * constraints on Apollo Lake SoC (some stepping affected), VTD could
 170          * not be enabled together with IPU. Doing so will override and disable
 171          * VTD while leaving CAPID0_A still reporting that VTD is available.
 172          * As in this case FSP will lock VTD to disabled state, we need to make
 173          * sure that DMAR table generation only happens when at least DEFVTBAR
 174          * is enabled. Otherwise the DMAR header will be generated while the
 175          * content of the table will be missing.
 176          */
 177
 178         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 179             !(MCHBAR32(DEFVTBAR) & VTBAR_ENABLED))
 180                 return current;
 181
 182         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 183         acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar);
 184         current += dmar->header.length;
 185         current = acpi_align_current(current);
 186         acpi_add_table(rsdp, dmar);
 187         current = acpi_align_current(current);
 188
 189         return current;
 190 }
 191
 192 void soc_power_states_generation(int core_id, int cores_per_package)
 193 {
 194         /* Generate P-state tables */
 195         generate_p_state_entries(core_id, cores_per_package);
 196
 197         /* Generate T-state tables */
 198         generate_t_state_entries(core_id, cores_per_package);
 199 }
 200
 201 static void acpigen_soc_get_dw0_in_local5(uintptr_t addr)
 202 {
 203         /*
 204          * Store (\_SB.GPC0 (addr), Local5)
 205          * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in
 206          * gpiolib.asl.
 207          */
 208         acpigen_write_store();
 209         acpigen_emit_namestring("\\_SB.GPC0");
 210         acpigen_write_integer(addr);
 211         acpigen_emit_byte(LOCAL5_OP);
 212 }
 213
 214 static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
 215 {
 216         assert(gpio_num < TOTAL_PADS);
 217         uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
 218
 219         acpigen_soc_get_dw0_in_local5(addr);
 220
 221         /* If (And (Local5, mask)) */
 222         acpigen_write_if_and(LOCAL5_OP, mask);
 223
 224         /* Store (One, Local0) */
 225         acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
 226
 227         /* Else */
 228         acpigen_write_else();
 229
 230         /* Store (Zero, Local0) */
 231         acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
 232
 233         acpigen_pop_len();      /* Else */
 234
 235         return 0;
 236 }
 237
 238 static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
 239 {
 240         assert(gpio_num < TOTAL_PADS);
 241         uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
 242
 243         acpigen_soc_get_dw0_in_local5(addr);
 244
 245         if (val) {
 246                 /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */
 247                 acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP);
 248         } else {
 249                 /* Not (PAD_CFG0_TX_STATE, Local6) */
 250                 acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP);
 251
 252                 /* And (Local5, Local6, Local5) */
 253                 acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
 254         }
 255
 256         /*
 257          * \_SB.SPC0 (addr, Local5)
 258          * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in
 259          * gpiolib.asl.
 260          */
 261         acpigen_emit_namestring("\\_SB.SPC0");
 262         acpigen_write_integer(addr);
 263         acpigen_emit_byte(LOCAL5_OP);
 264
 265         return 0;
 266 }
 267
 268 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 269 {
 270         return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE);
 271 }
 272
 273 int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
 274 {
 275         return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE);
 276 }
 277
 278 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 279 {
 280         return acpigen_soc_set_gpio_val(gpio_num, 1);
 281 }
 282
 283 int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 284 {
 285         return acpigen_soc_set_gpio_val(gpio_num, 0);
 286 }