src/soc/intel/apollolake/bootblock/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <bootblock_common.h>
   4 #include <cpu/x86/pae.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <gpio.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <intelblocks/fast_spi.h>
  10 #include <intelblocks/lpc_lib.h>
  11 #include <intelblocks/p2sb.h>
  12 #include <intelblocks/pcr.h>
  13 #include <intelblocks/rtc.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <intelblocks/pmclib.h>
  16 #include <intelblocks/tco.h>
  17 #include <intelblocks/uart.h>
  18 #include <soc/iomap.h>
  19 #include <soc/cpu.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/pm.h>
  24 #include <spi-generic.h>
  25
  26 static const struct pad_config tpm_spi_configs[] = {
  27 #if CONFIG(SOC_INTEL_GEMINILAKE)
  28         PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
  29 #else
  30         PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),        /* FST_SPI_CS2_N */
  31 #endif
  32 };
  33
  34 static void tpm_enable(void)
  35 {
  36         /* Configure gpios */
  37         gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
  38 }
  39
  40 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  41 {
  42         pci_devfn_t dev;
  43
  44         bootblock_systemagent_early_init();
  45
  46         p2sb_enable_bar();
  47         p2sb_configure_hpet();
  48
  49         /* Decode the ACPI I/O port range for early firmware verification.*/
  50         dev = PCH_DEV_PMC;
  51         pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
  52         pci_write_config16(dev, PCI_COMMAND,
  53                                 PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  54
  55         enable_rtc_upper_bank();
  56
  57         /* Call lib/bootblock.c main */
  58         bootblock_main_with_basetime(base_timestamp);
  59 }
  60
  61 static void enable_pmcbar(void)
  62 {
  63         pci_devfn_t pmc = PCH_DEV_PMC;
  64
  65         /* Set PMC base addresses and enable decoding. */
  66         pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS);
  67         pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
  68         pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
  69         pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
  70         pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
  71         pci_write_config16(pmc, PCI_COMMAND,
  72                                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  73                                 PCI_COMMAND_MASTER);
  74 }
  75
  76 void bootblock_soc_early_init(void)
  77 {
  78         enable_pmcbar();
  79
  80         /* Clear global reset promotion bit */
  81         pmc_global_reset_enable(0);
  82
  83         /* Prepare UART for serial console. */
  84         if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
  85                 uart_bootblock_init();
  86
  87         uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
  88                 LPC_IOE_EC_62_66;
  89
  90         const config_t *config = config_of_soc();
  91
  92
  93         if (config->lpc_ioe) {
  94                 io_enables = config->lpc_ioe & 0x3f0f;
  95                 lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377);
  96         } else {
  97                 /* IO Decode Range */
  98                 if (CONFIG(DRIVERS_UART_8250IO))
  99                         lpc_io_setup_comm_a_b();
 100         }
 101
 102         /* IO Decode Enable */
 103         lpc_enable_fixed_io_ranges(io_enables);
 104
 105         /* Program generic IO Decode Range */
 106         pch_enable_lpc();
 107
 108         if (CONFIG(TPM_ON_FAST_SPI))
 109                 tpm_enable();
 110
 111         enable_pm_timer_emulation();
 112
 113         fast_spi_early_init(SPI_BASE_ADDRESS);
 114
 115         fast_spi_cache_bios_region();
 116
 117         /* Initialize GPE for use as interrupt status */
 118         pmc_gpe_init();
 119
 120         /* Program TCO Timer Halt */
 121         tco_configure();
 122
 123         /* Use Nx and paging to prevent the frontend from writing back dirty
 124          * cache-as-ram lines to backing store that doesn't exist when the L1I
 125          * speculatively fetches a line that is sitting in the L1D. */
 126         if (CONFIG(PAGING_IN_CACHE_AS_RAM)) {
 127                 paging_set_nxe(1);
 128                 paging_set_default_pat();
 129                 paging_enable_for_car("pdpt", "pt");
 130         }
 131 }