src/soc/intel/apollolake/include/soc/pmc.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef _SOC_APOLLOLAKE_PMC_H_
   4 #define _SOC_APOLLOLAKE_PMC_H_
   5
   6 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
   7 #define PRSTS                   0x1000
   8 #define GEN_PMCON1              0x1020
   9 #define GEN_PMCON_A             GEN_PMCON1
  10 #define  COLD_BOOT_STS          (1 << 27)
  11 #define  COLD_RESET_STS         (1 << 26)
  12 #define  WARM_RESET_STS         (1 << 25)
  13 #define  GBL_RST_STS            (1 << 24)
  14 #define  SRS                    (1 << 20)
  15 #define  MS4V                   (1 << 18)
  16 #define  SUS_PWR_FLR            (1 << 16)
  17 #define  PWR_FLR                (1 << 14)
  18 #define  RPS                    (1 << 2)
  19 #define  SLEEP_AFTER_POWER_FAIL (1 << 0)
  20 #define GEN_PMCON1_CLR1_BITS    (COLD_BOOT_STS | COLD_RESET_STS | \
  21                                  WARM_RESET_STS | GBL_RST_STS | \
  22                                  SRS | MS4V)
  23 #define GEN_PMCON2              0x1024
  24 #define GEN_PMCON_B             GEN_PMCON2
  25 #define  LPC_LPB_CLK_CTRL       ((1 << 11) | (1 << 12) | (1 << 13))
  26 #define  BIOS_PCI_EXP_EN        (1 << 10)
  27 #define  PWRBTN_LVL             (1 <<  9)
  28 #define  SMI_LOCK               (1 <<  4)
  29 #define  PER_SMI_SEL_MASK       (3 <<  0)
  30 #define    SMI_RATE_64S         (0 <<  0)
  31 #define    SMI_RATE_32S         (1 <<  0)
  32 #define    SMI_RATE_16S         (2 <<  0)
  33 #define    SMI_RATE_8S          (3 <<  0)
  34
  35 #define GEN_PMCON3              0x1028
  36 #define  SLP_S3_ASSERT_WIDTH_SHIFT      10
  37 #define  SLP_S3_ASSERT_MASK     (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT)
  38 #define  SLP_S3_ASSERT_60_USEC  0x0
  39 #define  SLP_S3_ASSERT_1_MSEC   0x1
  40 #define  SLP_S3_ASSERT_50_MSEC  0x2
  41 #define  SLP_S3_ASSERT_2_SEC    0x3
  42 #define ETR                     0x1048
  43 #define CF9_LOCK                (1 << 31)
  44 #define  CF9_GLB_RST            (1 << 20)
  45 #define GPIO_GPE_CFG            0x1050
  46 #define  GPE0_DWX_MASK          0xf
  47 #define GPE0_DW_SHIFT(x)        (4 + 4*(x))
  48
  49 #if CONFIG(SOC_INTEL_GEMINILAKE)
  50 #define PMC_GPE_AUDIO_31_0      9
  51 #define PMC_GPE_N_95_64         8
  52 #define PMC_GPE_N_63_32         7
  53 #define PMC_GPE_N_31_0          6
  54 #define PMC_GPE_NW_127_96       5
  55 #define PMC_GPE_NW_95_64        4
  56 #define PMC_GPE_NW_63_32        3
  57 #define PMC_GPE_NW_31_0         2
  58 #define PMC_GPE_SCC_63_32       1
  59 #define PMC_GPE_SCC_31_0        0
  60 #else  /*For APL*/
  61 #define  PMC_GPE_SW_31_0        0
  62 #define  PMC_GPE_SW_63_32       1
  63 #define  PMC_GPE_NW_31_0        3
  64 #define  PMC_GPE_NW_63_32       4
  65 #define  PMC_GPE_NW_95_64       5
  66 #define  PMC_GPE_N_31_0         6
  67 #define  PMC_GPE_N_63_32        7
  68 #define  PMC_GPE_W_31_0         9
  69 #endif
  70
  71 #define IRQ_REG                 0x106C
  72 #define SCI_IRQ_ADJUST          24
  73 #define SCI_IRQ_SEL             (255 << SCI_IRQ_ADJUST)
  74 #define SCIS_IRQ9               9
  75 #define SCIS_IRQ10              10
  76 #define SCIS_IRQ11              11
  77 #define SCIS_IRQ20              20
  78 #define SCIS_IRQ21              21
  79 #define SCIS_IRQ22              22
  80 #define SCIS_IRQ23              23
  81
  82 #endif