src/soc/intel/apollolake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <cpu/cpu.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci_ops.h>
   7 #include <fsp/util.h>
   8 #include <intelblocks/systemagent.h>
   9 #include <soc/iomap.h>
  10 #include <soc/systemagent.h>
  11
  12 /*
  13  * SoC implementation
  14  *
  15  * Add all known fixed memory ranges for Host Controller/Memory
  16  * controller.
  17  */
  18 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  19 {
  20         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  21                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  22                                 "PCIEXBAR" },
  23                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  24         };
  25
  26         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  27                         ARRAY_SIZE(soc_fixed_resources));
  28
  29         /* Add VTd resources if VTd is enabled. These resources were
  30            set up by the FSP-S call. */
  31         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  32                 return;
  33
  34         if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) {
  35                 mmio_range(dev, *index, MCHBAR64(GFXVTBAR) & VTBAR_MASK, VTBAR_SIZE);
  36                 (*index)++;
  37         }
  38         if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) {
  39                 mmio_range(dev, *index, MCHBAR64(DEFVTBAR) & VTBAR_MASK, VTBAR_SIZE);
  40                 (*index)++;
  41         }
  42 }
  43
  44 int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
  45                         uint64_t *prmrr_mask)
  46 {
  47         const void *hob;
  48         size_t hob_size, prmrr_size;
  49         uint64_t phys_address_mask;
  50         const uint8_t prmrr_phys_base_guid[16] = {
  51                 0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f,
  52                 0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33
  53         };
  54         const uint8_t prmrr_size_guid[16] = {
  55                 0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42,
  56                 0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41
  57         };
  58
  59         hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid,
  60                         &hob_size);
  61         if (!hob) {
  62                 printk(BIOS_ERR, "Failed to locate PRMRR base hob\n");
  63                 return -1;
  64         }
  65         if (hob_size != sizeof(uint64_t)) {
  66                 printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
  67                 return -1;
  68         }
  69         *prmrr_base = *(uint64_t *)hob;
  70
  71         hob = fsp_find_extension_hob_by_guid(prmrr_size_guid,
  72                         &hob_size);
  73         if (!hob) {
  74                 printk(BIOS_ERR, "Failed to locate PRMRR size hob\n");
  75                 return -1;
  76         }
  77         if (hob_size != sizeof(uint64_t)) {
  78                 printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
  79                 return -1;
  80         }
  81         prmrr_size = *(uint64_t *)hob;
  82         phys_address_mask = (1ULL << cpu_phys_address_size()) - 1;
  83         *prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1);
  84
  85         return 0;
  86 }
  87
  88 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
  89 {
  90         /* Max 4GiB per rank, 2 ranks per channel. Intel Document: 332092-002 */
  91         return 8192;
  92 }