src/soc/intel/baytrail/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/romstage.h>
   4 #include <cbmem.h>
   5 #include <cpu/x86/mtrr.h>
   6 #include <cpu/x86/smm.h>
   7 #include <soc/iosf.h>
   8
   9 static uintptr_t smm_region_start(void)
  10 {
  11         return (iosf_bunit_read(BUNIT_SMRRL) << 20);
  12 }
  13
  14 static size_t smm_region_size(void)
  15 {
  16         return CONFIG_SMM_TSEG_SIZE;
  17 }
  18
  19 uintptr_t cbmem_top_chipset(void)
  20 {
  21         return smm_region_start();
  22 }
  23
  24 void smm_region(uintptr_t *start, size_t *size)
  25 {
  26         *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
  27         *size = smm_region_size();
  28 }
  29
  30 void fill_postcar_frame(struct postcar_frame *pcf)
  31 {
  32         /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
  33          * above top of the ram. This satisfies MTRR alignment requirement
  34          * with different TSEG size configurations.
  35          */
  36         const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
  37         postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
  38                                MTRR_TYPE_WRBACK);
  39 }