src/soc/intel/baytrail/scc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi_gnvs.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <reg_script.h>
   8
   9 #include <soc/iosf.h>
  10 #include <soc/device_nvs.h>
  11 #include <soc/ramstage.h>
  12
  13 static const struct reg_script scc_start_dll[] = {
  14         /* Configure master DLL. */
  15         REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000),
  16         /* Configure Swing,FSM for Master DLL */
  17         REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133),
  18         /* Run+Local Reset on Master DLL */
  19         REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933),
  20         REG_SCRIPT_END,
  21 };
  22
  23 static const struct reg_script scc_after_dll[] = {
  24         /* Configure Write Path */
  25         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad),
  26         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad),
  27         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad),
  28         /* Configure Read Path */
  29         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad),
  30         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad),
  31         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad),
  32         /* eMMC 4.5 TX and RX DLL */
  33         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d),
  34         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d),
  35         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d),
  36         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d),
  37         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d),
  38         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0),
  39         /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew  */
  40         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0),
  41         REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0),
  42         /*
  43          * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01
  44          * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01
  45          */
  46         REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5),
  47         /* Enable IOSF Snoop */
  48         REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)),
  49         /* SDIO 3V Support. */
  50         REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30),
  51         REG_SCRIPT_END,
  52 };
  53
  54 void baytrail_init_scc(void)
  55 {
  56         uint32_t dll_values;
  57
  58         printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
  59
  60         /* Common Sideband Initialization for SCC */
  61         reg_script_run(scc_start_dll);
  62
  63         /* Override Slave Path - populate DLL settings. */
  64         dll_values = iosf_score_read(0x496c) & 0x7ffff;
  65         dll_values |= iosf_score_read(0x4950) & ~0xfffff;
  66         iosf_score_write(0x4950, dll_values | (1 << 19));
  67
  68         reg_script_run(scc_after_dll);
  69 }
  70
  71 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
  72 {
  73         struct reg_script ops[] = {
  74                 /* Disable PCI interrupt, enable Memory and Bus Master */
  75                 REG_PCI_OR16(PCI_COMMAND,
  76                              PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
  77                 /* Enable ACPI mode */
  78                 REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
  79                             SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),
  80                 REG_SCRIPT_END
  81         };
  82         struct resource *bar;
  83         struct device_nvs *dev_nvs = acpi_get_device_nvs();
  84
  85         /* Save BAR0 and BAR1 to ACPI NVS */
  86         bar = probe_resource(dev, PCI_BASE_ADDRESS_0);
  87         if (bar)
  88                 dev_nvs->scc_bar0[nvs_index] = (u32)bar->base;
  89
  90         bar = probe_resource(dev, PCI_BASE_ADDRESS_1);
  91         if (bar)
  92                 dev_nvs->scc_bar1[nvs_index] = (u32)bar->base;
  93
  94         /* Device is enabled in ACPI mode */
  95         dev_nvs->scc_en[nvs_index] = 1;
  96
  97         /* Put device in ACPI mode */
  98         reg_script_run_on_dev(dev, ops);
  99 }