src/soc/intel/baytrail/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <arch/io.h>
   6 #include <device/pci_ops.h>
   7 #include <console/console.h>
   8 #include <cpu/x86/cache.h>
   9 #include <cpu/x86/smm.h>
  10 #include <cpu/intel/em64t100_save_state.h>
  11 #include <device/pci_def.h>
  12 #include <elog.h>
  13 #include <halt.h>
  14 #include <spi-generic.h>
  15 #include <smmstore.h>
  16
  17 #include <soc/iosf.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/nvs.h>
  21 #include <soc/device_nvs.h>
  22
  23 void southbridge_smi_set_eos(void)
  24 {
  25         enable_smi(EOS);
  26 }
  27
  28 static void busmaster_disable_on_bus(int bus)
  29 {
  30         int slot, func;
  31         unsigned int val;
  32         unsigned char hdr;
  33
  34         for (slot = 0; slot < 0x20; slot++) {
  35                 for (func = 0; func < 8; func++) {
  36                         u16 reg16;
  37                         pci_devfn_t dev = PCI_DEV(bus, slot, func);
  38
  39                         val = pci_read_config32(dev, PCI_VENDOR_ID);
  40
  41                         if (val == 0xffffffff || val == 0x00000000 ||
  42                             val == 0x0000ffff || val == 0xffff0000)
  43                                 continue;
  44
  45                         /* Disable Bus Mastering for this one device */
  46                         reg16 = pci_read_config16(dev, PCI_COMMAND);
  47                         reg16 &= ~PCI_COMMAND_MASTER;
  48                         pci_write_config16(dev, PCI_COMMAND, reg16);
  49
  50                         /* If this is a bridge, then follow it. */
  51                         hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
  52                         hdr &= 0x7f;
  53                         if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
  54                                 unsigned int buses;
  55                                 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
  56                                 busmaster_disable_on_bus((buses >> 8) & 0xff);
  57                         }
  58                 }
  59         }
  60 }
  61
  62 static void southbridge_smi_sleep(void)
  63 {
  64         uint32_t reg32;
  65         uint8_t slp_typ;
  66         uint16_t pmbase = get_pmbase();
  67
  68         /* First, disable further SMIs */
  69         disable_smi(SLP_SMI_EN);
  70
  71         /* Figure out SLP_TYP */
  72         reg32 = inl(pmbase + PM1_CNT);
  73         printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
  74         slp_typ = acpi_sleep_from_pm1(reg32);
  75
  76         /* Do any mainboard sleep handling */
  77         mainboard_smi_sleep(slp_typ);
  78
  79         /* Log S3, S4, and S5 entry */
  80         if (slp_typ >= ACPI_S3)
  81                 elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
  82
  83         /* Next, do the deed. */
  84         switch (slp_typ) {
  85         case ACPI_S0:
  86                 printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
  87                 break;
  88         case ACPI_S1:
  89                 printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
  90                 break;
  91         case ACPI_S3:
  92                 printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
  93
  94                 /* Invalidate the cache before going to S3 */
  95                 wbinvd();
  96                 break;
  97         case ACPI_S4:
  98                 printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
  99                 break;
 100         case ACPI_S5:
 101                 printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 102
 103                 /* Disable all GPE */
 104                 disable_all_gpe();
 105
 106                 /* Also iterates over all bridges on bus 0 */
 107                 busmaster_disable_on_bus(0);
 108                 break;
 109         default:
 110                 printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
 111                 break;
 112         }
 113
 114         /*
 115          * Write back to the SLP register to cause the originally intended event again.
 116          * We need to set BIT13 (SLP_EN) though to make the sleep happen.
 117          */
 118         enable_pm1_control(SLP_EN);
 119
 120         /* Make sure to stop executing code here for S3/S4/S5 */
 121         if (slp_typ >= ACPI_S3)
 122                 halt();
 123
 124         /*
 125          * In most sleep states, the code flow of this function ends at
 126          * the line above. However, if we entered sleep state S1 and wake
 127          * up again, we will continue to execute code in this function.
 128          */
 129         reg32 = inl(pmbase + PM1_CNT);
 130         if (reg32 & SCI_EN) {
 131                 /* The OS is not an ACPI OS, so we set the state to S0 */
 132                 disable_pm1_control(SLP_EN | SLP_TYP);
 133         }
 134 }
 135
 136 /*
 137  * Look for Synchronous IO SMI and use save state from that core in case
 138  * we are not running on the same core that initiated the IO transaction.
 139  */
 140 static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
 141 {
 142         em64t100_smm_state_save_area_t *state;
 143         int node;
 144
 145         /* Check all nodes looking for the one that issued the IO */
 146         for (node = 0; node < CONFIG_MAX_CPUS; node++) {
 147                 state = smm_get_save_state(node);
 148
 149                 /* Check for Synchronous IO (bit0==1) */
 150                 if (!(state->io_misc_info & (1 << 0)))
 151                         continue;
 152
 153                 /* Make sure it was a write (bit4==0) */
 154                 if (state->io_misc_info & (1 << 4))
 155                         continue;
 156
 157                 /* Check for APMC IO port */
 158                 if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
 159                         continue;
 160
 161                 /* Check AX against the requested command */
 162                 if ((state->rax & 0xff) != cmd)
 163                         continue;
 164
 165                 return state;
 166         }
 167
 168         return NULL;
 169 }
 170
 171 static void southbridge_smi_gsmi(void)
 172 {
 173         u32 *ret, *param;
 174         uint8_t sub_command;
 175         em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
 176
 177         if (!io_smi)
 178                 return;
 179
 180         /* Command and return value in EAX */
 181         ret = (u32 *)&io_smi->rax;
 182         sub_command = (uint8_t)(*ret >> 8);
 183
 184         /* Parameter buffer in EBX */
 185         param = (u32 *)&io_smi->rbx;
 186
 187         /* drivers/elog/gsmi.c */
 188         *ret = gsmi_exec(sub_command, param);
 189 }
 190
 191 void *acpi_get_device_nvs(void)
 192 {
 193         return (u8 *)gnvs + ALIGN_UP(sizeof(struct global_nvs), sizeof(uint64_t));
 194 }
 195
 196 /*
 197  * soc_legacy: A payload (Depthcharge) has indicated that the
 198  *   legacy payload (SeaBIOS) is being loaded. Switch devices that are
 199  *   in ACPI mode to PCI mode so that non-ACPI drivers may work.
 200  *
 201  */
 202 static void soc_legacy(void)
 203 {
 204         struct device_nvs *dev_nvs = acpi_get_device_nvs();
 205         u32 reg32;
 206
 207         /* LPE Device */
 208         if (dev_nvs->lpe_en) {
 209                 reg32 = iosf_port58_read(LPE_PCICFGCTR1);
 210                 reg32 &=
 211                 ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
 212                 iosf_port58_write(LPE_PCICFGCTR1, reg32);
 213         }
 214
 215         /* SCC Devices */
 216 #define SCC_ACPI_MODE_DISABLE(name_) \
 217         do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \
 218                 reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
 219                 reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
 220                 iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
 221         } } while (0)
 222
 223         SCC_ACPI_MODE_DISABLE(MMC);
 224         SCC_ACPI_MODE_DISABLE(SD);
 225         SCC_ACPI_MODE_DISABLE(SDIO);
 226
 227          /* LPSS Devices */
 228 #define LPSS_ACPI_MODE_DISABLE(name_) \
 229         do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \
 230                 reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
 231                 reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
 232                 iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \
 233         } } while (0)
 234
 235         LPSS_ACPI_MODE_DISABLE(SIO_DMA1);
 236         LPSS_ACPI_MODE_DISABLE(I2C1);
 237         LPSS_ACPI_MODE_DISABLE(I2C2);
 238         LPSS_ACPI_MODE_DISABLE(I2C3);
 239         LPSS_ACPI_MODE_DISABLE(I2C4);
 240         LPSS_ACPI_MODE_DISABLE(I2C5);
 241         LPSS_ACPI_MODE_DISABLE(I2C6);
 242         LPSS_ACPI_MODE_DISABLE(I2C7);
 243         LPSS_ACPI_MODE_DISABLE(SIO_DMA2);
 244         LPSS_ACPI_MODE_DISABLE(PWM1);
 245         LPSS_ACPI_MODE_DISABLE(PWM2);
 246         LPSS_ACPI_MODE_DISABLE(HSUART1);
 247         LPSS_ACPI_MODE_DISABLE(HSUART2);
 248         LPSS_ACPI_MODE_DISABLE(SPI);
 249 }
 250
 251 static void southbridge_smi_store(void)
 252 {
 253         u8 sub_command, ret;
 254         em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE);
 255         uint32_t reg_ebx;
 256
 257         if (!io_smi)
 258                 return;
 259         /* Command and return value in EAX */
 260         sub_command = (io_smi->rax >> 8) & 0xff;
 261
 262         /* Parameter buffer in EBX */
 263         reg_ebx = io_smi->rbx;
 264
 265         /* drivers/smmstore/smi.c */
 266         ret = smmstore_exec(sub_command, (void *)reg_ebx);
 267         io_smi->rax = ret;
 268 }
 269
 270 static void southbridge_smi_apmc(void)
 271 {
 272         uint8_t reg8;
 273
 274         reg8 = apm_get_apmc();
 275         switch (reg8) {
 276         case APM_CNT_ACPI_DISABLE:
 277                 disable_pm1_control(SCI_EN);
 278                 break;
 279         case APM_CNT_ACPI_ENABLE:
 280                 enable_pm1_control(SCI_EN);
 281                 break;
 282         case APM_CNT_ELOG_GSMI:
 283                 if (CONFIG(ELOG_GSMI))
 284                         southbridge_smi_gsmi();
 285                 break;
 286         case APM_CNT_LEGACY:
 287                 soc_legacy();
 288                 break;
 289         case APM_CNT_SMMSTORE:
 290                 if (CONFIG(SMMSTORE))
 291                         southbridge_smi_store();
 292                 break;
 293         }
 294
 295         mainboard_smi_apmc(reg8);
 296 }
 297
 298 static void southbridge_smi_pm1(void)
 299 {
 300         uint16_t pm1_sts = clear_pm1_status();
 301
 302         /* While OSPM is not active, poweroff immediately on a power button event */
 303         if (pm1_sts & PWRBTN_STS) {
 304                 /* Power button pressed */
 305                 elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
 306                 disable_pm1_control(-1UL);
 307                 enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
 308         }
 309 }
 310
 311 static void southbridge_smi_gpe0(void)
 312 {
 313         clear_gpe_status();
 314 }
 315
 316 static void southbridge_smi_tco(void)
 317 {
 318         uint32_t tco_sts = clear_tco_status();
 319
 320         /* Any TCO event? */
 321         if (!tco_sts)
 322                 return;
 323
 324         if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
 325                 /* Handle TCO timeout */
 326                 printk(BIOS_DEBUG, "TCO Timeout.\n");
 327         }
 328 }
 329
 330 static void southbridge_smi_periodic(void)
 331 {
 332         uint32_t reg32;
 333
 334         reg32 = inl(get_pmbase() + SMI_EN);
 335
 336         /* Are periodic SMIs enabled? */
 337         if ((reg32 & PERIODIC_EN) == 0)
 338                 return;
 339
 340         printk(BIOS_DEBUG, "Periodic SMI.\n");
 341 }
 342
 343 typedef void (*smi_handler_t)(void);
 344
 345 static const smi_handler_t southbridge_smi[32] = {
 346         NULL,                     /*  [0] reserved */
 347         NULL,                     /*  [1] reserved */
 348         NULL,                     /*  [2] BIOS_STS */
 349         NULL,                     /*  [3] LEGACY_USB_STS */
 350         southbridge_smi_sleep,    /*  [4] SLP_SMI_STS */
 351         southbridge_smi_apmc,     /*  [5] APM_STS */
 352         NULL,                     /*  [6] SWSMI_TMR_STS */
 353         NULL,                     /*  [7] reserved */
 354         southbridge_smi_pm1,      /*  [8] PM1_STS */
 355         southbridge_smi_gpe0,     /*  [9] GPE0_STS */
 356         NULL,                     /* [10] reserved */
 357         NULL,                     /* [11] reserved */
 358         NULL,                     /* [12] reserved */
 359         southbridge_smi_tco,      /* [13] TCO_STS */
 360         southbridge_smi_periodic, /* [14] PERIODIC_STS */
 361         NULL,                     /* [15] SERIRQ_SMI_STS */
 362         NULL,                     /* [16] SMBUS_SMI_STS */
 363         NULL,                     /* [17] LEGACY_USB2_STS */
 364         NULL,                     /* [18] INTEL_USB2_STS */
 365         NULL,                     /* [19] reserved */
 366         NULL,                     /* [20] PCI_EXP_SMI_STS */
 367         NULL,                     /* [21] reserved */
 368         NULL,                     /* [22] reserved */
 369         NULL,                     /* [23] reserved */
 370         NULL,                     /* [24] reserved */
 371         NULL,                     /* [25] reserved */
 372         NULL,                     /* [26] SPI_STS */
 373         NULL,                     /* [27] reserved */
 374         NULL,                     /* [28] PUNIT */
 375         NULL,                     /* [29] GUNIT */
 376         NULL,                     /* [30] reserved */
 377         NULL                      /* [31] reserved */
 378 };
 379
 380 void southbridge_smi_handler(void)
 381 {
 382         int i;
 383         uint32_t smi_sts;
 384
 385         /*
 386          * We need to clear the SMI status registers, or we won't see what's
 387          * happening in the following calls.
 388          */
 389         smi_sts = clear_smi_status();
 390
 391         /* Call SMI sub handler for each of the status bits */
 392         for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
 393                 if (!(smi_sts & (1 << i)))
 394                         continue;
 395
 396                 if (southbridge_smi[i] != NULL) {
 397                         southbridge_smi[i]();
 398                 } else {
 399                         printk(BIOS_DEBUG,
 400                                "SMI_STS[%d] occurred, but no handler available.\n", i);
 401                 }
 402         }
 403
 404         /*
 405          * The GPIO SMI events do not have a status bit in SMI_STS. Therefore,
 406          * these events need to be cleared and checked unconditionally.
 407          */
 408         mainboard_smi_gpi(clear_alt_status());
 409 }