src/soc/intel/baytrail/tsc_freq.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/x86/msr.h>
   4 #include <cpu/x86/tsc.h>
   5 #include <soc/msr.h>
   6
   7 unsigned int bus_freq_khz(void)
   8 {
   9         msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
  10         switch (clk_info.lo & 0x3) {
  11         case 0:
  12                 return 83333;
  13         case 1:
  14                 return 100000;
  15         case 2:
  16                 return 133333;
  17         case 3:
  18                 return 116666;
  19         default:
  20                 return 0;
  21         }
  22 }
  23
  24 unsigned long tsc_freq_mhz(void)
  25 {
  26         msr_t platform_info;
  27         unsigned int bclk_khz = bus_freq_khz();
  28
  29         if (!bclk_khz)
  30                 return 0;
  31
  32         platform_info = rdmsr(MSR_PLATFORM_INFO);
  33         return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
  34 }
  35
  36 void set_max_freq(void)
  37 {
  38         msr_t perf_ctl;
  39         msr_t msr;
  40
  41         /* Enable speed step. */
  42         msr = rdmsr(IA32_MISC_ENABLE);
  43         msr.lo |= (1 << 16);
  44         wrmsr(IA32_MISC_ENABLE, msr);
  45
  46         /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
  47         * the PERF_CTL. */
  48         msr = rdmsr(MSR_IACORE_RATIOS);
  49         perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
  50         /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
  51         * the PERF_CTL. */
  52         msr = rdmsr(MSR_IACORE_VIDS);
  53         perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
  54         perf_ctl.hi = 0;
  55
  56         wrmsr(IA32_PERF_CTL, perf_ctl);
  57 }