src/soc/intel/braswell/smbus.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <soc/iomap.h>
   6 #include <soc/pci_devs.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_type.h>
   9 #include <device/pci_ops.h>
  10 #include <device/smbus_host.h>
  11 #include <soc/smbus.h>
  12
  13 int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
  14 {
  15         const pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
  16
  17         u32 smbase;
  18         u32 smb_ctrl_reg;
  19         int status;
  20
  21         /* SMBus I/O BAR */
  22         smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
  23
  24         /* Enable I2C_EN bit in HOSTC register */
  25         smb_ctrl_reg = pci_read_config32(dev, HOSTC);
  26         pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
  27
  28         status = do_i2c_block_write(smbase, addr, bytes, buf);
  29
  30         /* Restore I2C_EN bit */
  31         pci_write_config32(dev, HOSTC, smb_ctrl_reg);
  32
  33         return status;
  34 }