mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / common / block / cse / Makefile.mk
blobd41d7354622aa197cfa0bee28dbfe495c0cf790d
1 ## SPDX-License-Identifier: GPL-2.0-only
2 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
3 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
4 romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
5 ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
6 ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite_cmos.c
7 romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite_cmos.c
8 ramstage-$(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) += cse_spec.c
9 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
10 smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
11 ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
12 romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c
14 romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) += cse_sync_payload.c
16 ifeq ($(CONFIG_STITCH_ME_BIN),y)
18 CSE_BP1_BIN := $(objcse)/cse_bp1.bin
19 CSE_BP2_BIN := $(objcse)/cse_bp2.bin
20 CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin
21 CSE_RW_FILE := $(CSE_BP2_BIN)
23 CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION))
24 ifeq ($(CONFIG_CSE_BPDT_VERSION),)
25 $(error "CONFIG_CSE_BPDT_VERSION is not set!")
26 endif
28 CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE))
29 CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE))
31 get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET))
33 CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START)
34 CSE_BP1_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RO_START)
35 CSE_BP1_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RO_SIZE)
36 CSE_BP2_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_RW_START)
37 CSE_BP2_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_RW_SIZE)
38 CSE_DP_OFFSET=$(call get_cse_region_offset,FMAP_SECTION_CSE_DATA_START)
39 CSE_DP_SIZE=$(call get_fmap_value,FMAP_SECTION_CSE_DATA_SIZE)
41 .PHONY: cse_inputs
42 cse_inputs: $(cse_input_files)
44 $(cse_decomp_files): $(CSE_FPT_INPUT) $(CSE_FPT)
45 printf " DUMP $(@F)\n"
46 $(CSE_FPT) $< dump -o $(objcse) -n $(@F) > /dev/null
48 define cse_add_ingredient
49 $(if $($(2)-file), \
50 printf " CSEADD $(2) ($($(2)-file)) -> $(1)\n";
51 $(CSE_SERGER) $@ add -n $(2) -f $($(2)-file) > /dev/null,
52 printf " CSEADD $(2) (dummy) -> $(1)\n";
53 $(CSE_SERGER) $@ add -n $(2) > /dev/null)
54 endef
56 $(objcse)/cse_%.bin: $(CSE_SERGER) cse_inputs $(cse_decomp_files)
57 printf " CREATE $(@F) (version $(CSE_BPDT_VERSION))\n"
58 $(CSE_SERGER) $@ create-bpdt -v $(CSE_BPDT_VERSION) > /dev/null
59 $(foreach ingredient,$(cse_$*_ingredients),\
60 $(call cse_add_ingredient,$(@F),$(ingredient));)
62 $(OBJ_ME_BIN): $(CSE_BP1_BIN) $(CSE_BP2_BIN) $(CSE_DATA_INPUT) $(obj)/fmap_config.h
63 printf " CREATE $(@F)\n"
64 $(CSE_SERGER) $@ create-cse-region -v $(CSE_BPDT_VERSION) \
65 --bp1 $(CSE_BP1_OFFSET):$(CSE_BP1_SIZE) --bp1_file $(CSE_BP1_BIN) \
66 --bp2 $(CSE_BP2_OFFSET):$(CSE_BP2_SIZE) --bp2_file $(CSE_BP2_BIN) \
67 --dp $(CSE_DP_OFFSET):$(CSE_DP_SIZE) --dp_file $(CSE_DATA_INPUT) > /dev/null
69 endif
71 ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y)
73 ifneq ($(CONFIG_STITCH_ME_BIN),y)
75 ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"")
76 $(error "CSE RW file path is missing and need to be set by mainboard config")
77 endif
78 CSE_RW_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
80 endif
82 CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME))
84 regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B
86 cbfs-files-y += $(CSE_LITE_ME_RW)
87 $(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE)
88 $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW)
89 $(CSE_LITE_ME_RW)-type := raw
90 ifeq ($(CONFIG_SOC_INTEL_CSE_LITE_COMPRESS_ME_RW),y)
91 $(CSE_LITE_ME_RW)-compression := LZMA
92 endif
94 INPUT_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE))
95 TEMP_FILE := $(shell mktemp)
96 OFFSETS := 16 18 20 22 # Offsets for CSE version components
97 VERSIONS := CSE_VERSION_MAJOR CSE_VERSION_MINOR CSE_VERSION_HOTFIX CSE_VERSION_BUILD
98 INDEXES := $(shell seq 1 $(words $(OFFSETS)))
100 $(obj)/cse_rw.version:
101 $(foreach index,$(INDEXES), \
102 $(shell dd if=$(INPUT_FILE) of=$(TEMP_FILE) bs=1 skip=$(word $(index),$(OFFSETS)) count=2 status=none) \
103 $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c1-2))) ) \
105 rm -f $(TEMP_FILE)
106 $(eval CSE_RW_CBFS_VERSION := $(shell printf "%d.%d.%d.%d" $(CSE_VERSION_MAJOR)$(CSE_VERSION_MINOR)$(CSE_VERSION_HOTFIX)$(CSE_VERSION_BUILD)))
107 @echo '$(CSE_RW_CBFS_VERSION)' > $@
109 CSE_RW_VERSION = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME))
110 regions-for-file-$(CSE_RW_VERSION) = FW_MAIN_A,FW_MAIN_B
111 cbfs-files-y += $(CSE_RW_VERSION)
112 $(CSE_RW_VERSION)-file := $(obj)/cse_rw.version
113 $(CSE_RW_VERSION)-name := $(CSE_RW_VERSION)
114 $(CSE_RW_VERSION)-type := raw
116 endif
118 ifeq ($(CONFIG_SOC_INTEL_CSE_SUB_PART_UPDATE),y)
120 CSE_IOM_FILE = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE))
121 CSE_IOM = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME))
122 regions-for-file-$(CSE_IOM) = FW_MAIN_A,FW_MAIN_B,COREBOOT
123 cbfs-files-y += $(CSE_IOM)
124 $(CSE_IOM)-file := $(CSE_IOM_FILE)
125 $(CSE_IOM)-name := $(CSE_IOM)
126 $(CSE_IOM)-type := raw
128 CSE_NPHY_FILE = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE))
129 CSE_NPHY = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME))
130 regions-for-file-$(CSE_NPHY) = FW_MAIN_A,FW_MAIN_B,COREBOOT
131 cbfs-files-y += $(CSE_NPHY)
132 $(CSE_NPHY)-file := $(CSE_NPHY_FILE)
133 $(CSE_NPHY)-name := $(CSE_NPHY)
134 $(CSE_NPHY)-type := raw
135 endif