src/soc/intel/common/block/include/intelblocks/acpi.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef SOC_INTEL_COMMON_BLOCK_ACPI_H
   4 #define SOC_INTEL_COMMON_BLOCK_ACPI_H
   5
   6 #include <acpi/acpi.h>
   7 #include <device/device.h>
   8 #include <intelblocks/cpulib.h>
   9 #include <soc/pm.h>
  10 #include <stdint.h>
  11
  12 /* CPU Types */
  13 enum core_type {
  14         CPUID_RESERVED_1 = 0x10,
  15         CPUID_CORE_TYPE_INTEL_ATOM = 0x20,
  16         CPUID_RESERVED_2 = 0x30,
  17         CPUID_CORE_TYPE_INTEL_CORE = 0x40,
  18         CPUID_UNKNOWN = 0xff,
  19 };
  20
  21 unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current);
  22
  23 /* Generates ACPI code to define _CPC control method */
  24 void acpigen_write_CPPC_hybrid_method(int core_id);
  25
  26 /* Forward declare the power state struct here */
  27 struct chipset_power_state;
  28
  29 /* Forward  declare the global nvs structure here */
  30 struct global_nvs;
  31
  32 /* Return ACPI name for this device */
  33 const char *soc_acpi_name(const struct device *dev);
  34
  35 /* Read the scis from soc specific register. Returns int scis value */
  36 uint32_t soc_read_sci_irq_select(void);
  37
  38 /* Write the scis from soc specific register. */
  39 void soc_write_sci_irq_select(uint32_t scis);
  40
  41 /* _CST MWAIT resource used by cstate_map. */
  42 #define MWAIT_RES(state, sub_state)                         \
  43         {                                                   \
  44                 .addrl = (((state) << 4) | (sub_state)),    \
  45                 .space_id = ACPI_ADDRESS_SPACE_FIXED,       \
  46                 .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
  47                 .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
  48                 .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
  49         }
  50
  51 /*
  52  * get_cstate_map returns a table of processor specific acpi_cstate_t entries
  53  * and number of entries in the table
  54  */
  55 const acpi_cstate_t *soc_get_cstate_map(size_t *num_entries);
  56
  57 /*
  58  * get_tstate_map returns a table of processor specific acpi_tstate_t entries
  59  * and number of entries in the table
  60  */
  61 acpi_tstate_t *soc_get_tss_table(int *entries);
  62
  63 /*
  64  * Chipset specific quirks for the wake enable bits.
  65  */
  66 void acpi_fill_soc_wake(uint32_t *pm1_en, uint32_t *gpe0_en,
  67                         const struct chipset_power_state *ps);
  68
  69 /* Chipset specific settings for filling up dmar table */
  70 unsigned long sa_write_acpi_tables(const struct device *dev,
  71                                    unsigned long current,
  72                                    struct acpi_rsdp *rsdp);
  73
  74 /* Return the polarity flag for SCI IRQ */
  75 int soc_madt_sci_irq_polarity(int sci);
  76
  77 /* Generate P-state tables */
  78 void generate_p_state_entries(int core, int cores_per_package);
  79
  80 /* Generate T-state tables */
  81 void generate_t_state_entries(int core, int cores_per_package);
  82
  83 /*
  84  * soc specific power states generation. We need this to be defined by soc
  85  * as the state generations varies in chipsets e.g. APL generates T and P
  86  * states while SKL generates  * P state only depending on a devicetree config
  87  */
  88 void soc_power_states_generation(int core_id, int cores_per_package);
  89
  90 /*
  91  * Common function to calculate the power ratio for power state generation
  92  */
  93 int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio);
  94
  95
  96 /*
  97  * Return the number of table entries and takes a pointer to an array of ioapic bases.
  98  */
  99 size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]);
 100
 101 struct soc_pmc_lpm {
 102         unsigned int num_substates;
 103         unsigned int num_req_regs;
 104         unsigned int lpm_ipc_offset;
 105         unsigned int req_reg_stride;
 106         uint8_t lpm_enable_mask;
 107 };
 108
 109 /* Generate an Intel Power Engine ACPI device */
 110 void generate_acpi_power_engine(void);
 111
 112 /* Generate an Intel Power Engine ACPI device that supports exposing LPM
 113    substate requirements */
 114 void generate_acpi_power_engine_with_lpm(const struct soc_pmc_lpm *lpm);
 115
 116 /* Fill SSDT for SGX status, EPC base and length */
 117 void sgx_fill_ssdt(void);
 118
 119 /*
 120  * This function returns the CPU type (big or small) of the CPU that it is executing
 121  * on. It is designed to be called after MP initialization. If the SoC selects
 122  * SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID, then this function must be implemented,
 123  * and will be called from set_cpu_type().
 124  */
 125 enum core_type get_soc_cpu_type(void);
 126
 127 /* Check if CPU supports Nominal frequency or not */
 128 bool soc_is_nominal_freq_supported(void);
 129
 130 /* Min sleep state per device*/
 131 struct min_sleep_state {
 132         uint8_t pci_dev;
 133         enum acpi_device_sleep_states min_sleep_state;
 134 };
 135
 136 /* Updates core type into 'struct cpu_info' */
 137 void set_dev_core_type(void);
 138
 139 /*
 140  * This SOC callback returns an array that maps devices to their min sleep state.
 141  * Example:
 142  *
 143  * static struct min_sleep_state min_pci_sleep_states[] = {
 144  *      { SA_DEVFN_ROOT,        ACPI_DEVICE_SLEEP_D3 },
 145  *      { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 },
 146  *      { SA_DEVFN_IGD,         ACPI_DEVICE_SLEEP_D3 },
 147  *      ...
 148  * };
 149  *
 150  * const struct pad_config *variant_early_gpio_table(size_t *num)
 151  * {
 152  *      *num = ARRAY_SIZE(early_gpio_table);
 153  *      return early_gpio_table;
 154  * }
 155  *
 156  */
 157 struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size);
 158
 159 #endif                          /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */