mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / common / block / include / intelblocks / gspi.h
blobe98a799c1cb2c0f3c7e6856caa554b9e127f1261
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef SOC_INTEL_COMMON_BLOCK_GSPI_H
4 #define SOC_INTEL_COMMON_BLOCK_GSPI_H
6 #include <spi-generic.h>
7 #include <stdint.h>
9 /* GSPI controller structure to allow SoCs to define bus-controller mapping. */
10 extern const struct spi_ctrlr gspi_ctrlr;
12 struct gspi_cfg {
13 /* Bus speed in MHz. */
14 uint32_t speed_mhz;
15 /* Bus should be enabled prior to ramstage with temporary base. */
16 uint8_t early_init;
19 /* GSPI controller APIs. */
20 void gspi_early_bar_init(void);
22 /* SoC-callbacks */
24 * Map given GSPI bus number to devfn.
25 * Return value:
26 * -1 = error
27 * otherwise, devfn(>=0) corresponding to GSPI bus number.
29 int gspi_soc_bus_to_devfn(unsigned int gspi_bus);
32 * SoC-provided callback for getting configuration of SPI bus. Driver provides
33 * weak implementation with default SPI-bus configuration.
35 * Return value:
36 * 0 = Success
37 * -1 = Error
39 int gspi_get_soc_spi_cfg(unsigned int bus, struct spi_cfg *cfg);
41 #endif /* SOC_INTEL_COMMON_BLOCK_GSPI_H */