src/soc/intel/common/block/include/intelblocks/mmc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOC_INTEL_COMMON_BLOCK_MMC_H
   4 #define SOC_INTEL_COMMON_BLOCK_MMC_H
   5
   6 #include <stdint.h>
   7
   8 /*
   9  * Structure for the following delay registers
  10  * emmc_tx_data_cntl1: Tx Delay Control 1 (Tx_DATA_dly_1)-Offset 824h
  11  * emmc_tx_data_cntl2: Tx Delay Control 2 (Tx_DATA_dly_2)-Offset 828h
  12  * emmc_rx_cmd_data_cntl1: Rx CMD Data Delay Control 1
  13  *                                      (Rx_CMD_Data_dly_1)-Offset 82Ch
  14  * emmc_rx_cmd_data_cntl2: Rx CMD Data Path Delay Control 2
  15  *                                      (Rx_CMD_Data_dly_2)-Offset 834h
  16  * emmc_rx_strobe_cntl: Rx Strobe Delay Control
  17  *                                      (Rx_Strobe_Ctrl_Path)-Offset 830h
  18  * emmc_tx_cmd_cntl: Tx CMD Delay Control (Tx_CMD_dly)-Offset 820h
  19  */
  20 struct mmc_dll_params {
  21         uint32_t emmc_tx_data_cntl1;
  22         uint32_t emmc_tx_data_cntl2;
  23         uint32_t emmc_rx_cmd_data_cntl1;
  24         uint32_t emmc_rx_cmd_data_cntl2;
  25         uint32_t emmc_rx_strobe_cntl;
  26         uint32_t emmc_tx_cmd_cntl;
  27 };
  28
  29 /*
  30  * SOC specific API to get mmc min max frequencies.
  31  * returns 0, if able to get f_min, f_max; otherwise returns -1
  32  */
  33 int soc_get_mmc_frequencies(uint32_t *f_min, uint32_t *f_max);
  34 /*
  35  * SOC specific API to configure mmc gpios.
  36  * returns 0, if able to configure gpios; otherwise returns -1
  37  */
  38 int soc_configure_mmc_gpios(void);
  39 /*
  40  * SOC specific API to get mmc delay register settings.
  41  * returns 0, if able to get register settings; otherwise returns -1
  42  */
  43 int soc_get_mmc_dll(struct mmc_dll_params *params);
  44 /*
  45  * Set mmc delay register settings.
  46  * bar: eMMC controller MMIO base address.
  47  * returns 0, if able to set register settings; otherwise returns -1
  48  */
  49 int set_mmc_dll(void *bar);
  50
  51 #define EMMC_TX_CMD_CNTL_OFFSET                 0x820
  52 #define EMMC_TX_DATA_CNTL1_OFFSET               0x824
  53 #define EMMC_TX_DATA_CNTL2_OFFSET               0x828
  54 #define EMMC_RX_CMD_DATA_CNTL1_OFFSET           0x82C
  55 #define EMMC_RX_STROBE_CNTL_OFFSET              0x830
  56 #define EMMC_RX_CMD_DATA_CNTL2_OFFSET           0x834
  57
  58 #if CONFIG(SOC_INTEL_COMMON_EARLY_MMC_WAKE)
  59 /*
  60  * Following should be defined in soc/iomap.h
  61  * PRERAM_MMC_BASE_ADDRESS - Provide an address to setup emmc controller's
  62                         PCI BAR.
  63  */
  64
  65 /*
  66  * Initializes sdhci / mmc controller and sends CMD0, CMD1 to emmc card.
  67  * In case of success: It returns 0 and adds cbmem entry CBMEM_ID_MMC_STATUS
  68  * and sets it to 1. Payload can start by sending CMD1, there is no need to
  69  * send CMD0 and wait for the card to be ready.
  70  * In case of failure: It returns -1 and doesn't add cbmem entry. Payload
  71  * should do complete initialization starting with CMD0.
  72  */
  73 int early_mmc_wake_hw(void);
  74 #else
  75 static inline int early_mmc_wake_hw(void)
  76 {
  77         return -1;
  78 }
  79 #endif /* CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE */
  80 #endif /* SOC_INTEL_COMMON_BLOCK_MMC_H */