src/soc/intel/common/block/smbus/smbus.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/smbus.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <soc/smbus.h>
   8 #include <device/smbus_host.h>
   9 #include <intelblocks/tco.h>
  10 #include <southbridge/intel/common/smbus_ops.h>
  11 #include "smbuslib.h"
  12
  13 static void pch_smbus_init(struct device *dev)
  14 {
  15         struct resource *res;
  16
  17         /* Enable clock gating */
  18         pci_update_config32(dev, 0x80,
  19                 ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)), 0);
  20
  21         /* Set Receive Slave Address */
  22         res = probe_resource(dev, PCI_BASE_ADDRESS_4);
  23         if (res)
  24                 smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
  25 }
  26
  27 /*
  28  * `finalize_smbus` function is native implementation of equivalent events
  29  * performed by each FSP NotifyPhase() API invocations.
  30  *
  31  * Operations are:
  32  * 1. TCO Lock.
  33  */
  34 static void finalize_smbus(struct device *dev)
  35 {
  36         if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
  37                 tco_lockdown();
  38 }
  39
  40 struct device_operations smbus_ops = {
  41         .read_resources         = smbus_read_resources,
  42         .set_resources          = pci_dev_set_resources,
  43         .enable_resources       = pci_dev_enable_resources,
  44         .scan_bus               = scan_smbus,
  45         .init                   = pch_smbus_init,
  46         .ops_pci                = &pci_dev_ops_pci,
  47         .ops_smbus_bus          = &lops_smbus_bus,
  48         .final                  = finalize_smbus,
  49 };
  50
  51 static const unsigned short pci_device_ids[] = {
  52         PCI_DID_INTEL_PTL_SMBUS,
  53         PCI_DID_INTEL_LNL_SMBUS,
  54         PCI_DID_INTEL_MTL_SMBUS,
  55         PCI_DID_INTEL_RPP_P_SMBUS,
  56         PCI_DID_INTEL_RPP_S_SMBUS,
  57         PCI_DID_INTEL_APL_SMBUS,
  58         PCI_DID_INTEL_GLK_SMBUS,
  59         PCI_DID_INTEL_CNL_SMBUS,
  60         PCI_DID_INTEL_CNP_H_SMBUS,
  61         PCI_DID_INTEL_EBG_SMBUS,
  62         PCI_DID_INTEL_LWB_SMBUS_SUPER,
  63         PCI_DID_INTEL_LWB_SMBUS,
  64         PCI_DID_INTEL_ICP_LP_SMBUS,
  65         PCI_DID_INTEL_CMP_SMBUS,
  66         PCI_DID_INTEL_CMP_H_SMBUS,
  67         PCI_DID_INTEL_TGP_LP_SMBUS,
  68         PCI_DID_INTEL_TGP_H_SMBUS,
  69         PCI_DID_INTEL_MCC_SMBUS,
  70         PCI_DID_INTEL_JSP_SMBUS,
  71         PCI_DID_INTEL_ADP_P_SMBUS,
  72         PCI_DID_INTEL_ADP_S_SMBUS,
  73         PCI_DID_INTEL_ADP_M_N_SMBUS,
  74         PCI_DID_INTEL_DNV_SMBUS_LEGACY,
  75         0
  76 };
  77
  78 static const struct pci_driver pch_smbus __pci_driver = {
  79         .ops     = &smbus_ops,
  80         .vendor  = PCI_VID_INTEL,
  81         .devices         = pci_device_ids,
  82 };