src/soc/intel/denverton_ns/bootblock/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <bootblock_common.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <FsptUpd.h>
   8 #include <intelblocks/fast_spi.h>
   9 #include <soc/bootblock.h>
  10 #include <soc/pci_devs.h>
  11 #include <soc/systemagent.h>
  12 #include <spi-generic.h>
  13 #include <stdint.h>
  14 #include <console/console.h>
  15
  16 const FSPT_UPD temp_ram_init_params = {
  17         .FspUpdHeader = {
  18                         .Signature = 0x545F445055564E44ULL,
  19                         .Revision = 1,
  20                         .Reserved = {0},
  21         },
  22         .FsptCoreUpd = {
  23                         /*
  24                          * It is a requirement for firmware to have Firmware Interface Table
  25                          * (FIT), which contains pointers to each microcode update.
  26                          * The microcode update is loaded for all logical processors before
  27                          * cpu reset vector.
  28                          *
  29                          * All SoC since Gen-4 has above mechanism in place to load microcode
  30                          * even before hitting CPU reset vector. Hence skipping FSP-T loading
  31                          * microcode after CPU reset by passing '0' value to
  32                          * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
  33                          */
  34                         .MicrocodeRegionBase = 0,
  35                         .MicrocodeRegionLength = 0,
  36                         .CodeRegionBase =
  37                                 (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
  38                         .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
  39                         .Reserved1 = {0},
  40         },
  41         .FsptConfig = {
  42                         .PcdFsptPort80RouteDisable = 0,
  43                         .ReservedTempRamInitUpd = {0},
  44         },
  45         .UnusedUpdSpace0 = {0},
  46         .UpdTerminator = 0x55AA,
  47 };
  48
  49 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  50 {
  51         /* Call lib/bootblock.c main */
  52         bootblock_main_with_basetime(base_timestamp);
  53 };
  54
  55 static void sanity_check_pci_mmconf(void)
  56 {
  57         u32 pciexbar, base = 0, length = 0;
  58
  59         pciexbar = pci_io_read_config32(PCH_SA_DEV, PCIEXBAR);
  60         assert(pciexbar & (1 << 0));
  61
  62         switch (pciexbar & MASK_PCIEXBAR_LENGTH) {
  63         case MASK_PCIEXBAR_LENGTH_256M:
  64                 base = pciexbar & MASK_PCIEXBAR_256M;
  65                 length = 256;
  66                 break;
  67         case MASK_PCIEXBAR_LENGTH_128M:
  68                 base = pciexbar & MASK_PCIEXBAR_128M;
  69                 length = 128;
  70                 break;
  71         case MASK_PCIEXBAR_LENGTH_64M:
  72                 base = pciexbar & MASK_PCIEXBAR_64M;
  73                 length = 64;
  74                 break;
  75         }
  76
  77         assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS);
  78         assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER);
  79 }
  80
  81 void bootblock_soc_early_init(void)
  82 {
  83 #if (CONFIG(CONSOLE_SERIAL))
  84         early_uart_init();
  85 #endif
  86         fast_spi_early_init(DEFAULT_SPI_BASE);
  87 };
  88
  89 void bootblock_soc_init(void)
  90 {
  91         sanity_check_pci_mmconf();
  92
  93         if (CONFIG(BOOTBLOCK_CONSOLE))
  94                 printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
  95 };