src/soc/intel/denverton_ns/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H
   4 #define SOC_INTEL_DENVERTON_NS_CHIP_H
   5
   6 #include <stdint.h>
   7
   8 struct soc_intel_denverton_ns_config {
   9         /**
  10          * Interrupt Routing configuration
  11          * If bit7 is 1, the interrupt is disabled.
  12          */
  13         uint8_t pirqa_routing;
  14         uint8_t pirqb_routing;
  15         uint8_t pirqc_routing;
  16         uint8_t pirqd_routing;
  17         uint8_t pirqe_routing;
  18         uint8_t pirqf_routing;
  19         uint8_t pirqg_routing;
  20         uint8_t pirqh_routing;
  21
  22         /**
  23          * Device Interrupt Routing configuration
  24          * Interrupt Pin x Route.
  25          * 0h = PIRQA#
  26          * 1h = PIRQB#
  27          * 2h = PIRQC#
  28          * 3h = PIRQD#
  29          * 4h = PIRQE#
  30          * 5h = PIRQF#
  31          * 6h = PIRQG#
  32          * 7h = PIRQH#
  33          */
  34         uint16_t ir00_routing;
  35         uint16_t ir01_routing;
  36         uint16_t ir02_routing;
  37         uint16_t ir03_routing;
  38         uint16_t ir04_routing;
  39         uint16_t ir05_routing;
  40         uint16_t ir06_routing;
  41         uint16_t ir07_routing;
  42         uint16_t ir08_routing;
  43         uint16_t ir09_routing;
  44         uint16_t ir10_routing;
  45         uint16_t ir11_routing;
  46         uint16_t ir12_routing;
  47
  48         /**
  49         * Device Interrupt Polarity Control
  50         * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  51         * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  52         * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  53         * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
  54         */
  55         uint32_t ipc0;
  56         uint32_t ipc1;
  57         uint32_t ipc2;
  58         uint32_t ipc3;
  59
  60         /* TCC activation offset */
  61         uint32_t tcc_offset;
  62 };
  63
  64 typedef struct soc_intel_denverton_ns_config config_t;
  65
  66 #endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */