1 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 #include <cpu/x86/smm.h>
7 #include <device/device.h>
8 #include <device/mmio.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <intelblocks/pmc.h>
12 #include <soc/iomap.h>
15 #include <soc/pci_devs.h>
16 #include <soc/ramstage.h>
18 static void pch_power_options(struct device
*dev
) { /* TODO */ }
20 /* Fill up PMC resource structure */
21 int pmc_soc_get_resources(struct pmc_resource_config
*cfg
)
23 cfg
->pwrmbase_offset
= PMC_PWRM_BASE
;
24 cfg
->pwrmbase_addr
= DEFAULT_PWRM_BASE
;
25 cfg
->pwrmbase_size
= DEFAULT_PWRM_SIZE
;
26 cfg
->abase_offset
= PMC_ACPI_BASE
;
27 cfg
->abase_addr
= DEFAULT_PMBASE
;
28 cfg
->abase_size
= DEFAULT_PMBASE_SIZE
;
33 static void pch_set_acpi_mode(void)
35 if (!acpi_is_wakeup_s3()) {
36 apm_control(APM_CNT_ACPI_DISABLE
);
40 void pmc_soc_init(struct device
*dev
)
42 uint32_t pwrm_base
= pci_read_config32(dev
, PMC_PWRM_BASE
) & MASK_PMC_PWRM_BASE
;
44 printk(BIOS_DEBUG
, "pch: %s\n", __func__
);
46 /* Set the value for PCI command register. */
47 pci_write_config16(dev
, PCI_COMMAND
, PCI_COMMAND_MASTER
|
51 /* Setup power options. */
52 pch_power_options(dev
);
54 /* Configure ACPI mode. */
58 * Disable ACPI PM timer based on Kconfig
60 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
61 * Disabling ACPI PM timer also switches off TCO.
63 if (!CONFIG(USE_PM_ACPI_TIMER
))
64 setbits8((volatile void *)(uintptr_t)(pwrm_base
+ PCH_PWRM_ACPI_TMR_CTL
),