mb/system76/cml-u/dt: Make use of chipset devicetree
[coreboot.git] / src / soc / intel / denverton_ns / sata.c
blob3fb5d75c324cd5bbf6709604772780ab976ad52b
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <device/pci_ids.h>
10 #include <soc/pci_devs.h>
11 #include <soc/ramstage.h>
12 #include <soc/sata.h>
14 #include "chip.h"
16 static void sata_init(struct device *dev)
18 u32 reg32;
19 u32 abar;
21 printk(BIOS_DEBUG, "SATA: Initializing...\n");
23 /* SATA configuration is handled by the FSP */
25 /* Enable BARs */
26 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
27 PCI_COMMAND_MEMORY |
28 PCI_COMMAND_IO);
30 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
32 /* Set the controller mode */
33 reg32 = pci_read_config32(dev, SATAGC);
34 reg32 &= ~SATAGC_AHCI;
35 pci_write_config32(dev, SATAGC, reg32);
37 /* Initialize AHCI memory-mapped space */
38 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
39 printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
41 /* Enable AHCI Mode */
42 reg32 = read32((void *)(abar + 0x04));
43 reg32 |= (1 << 31);
44 write32((void *)(abar + 0x04), reg32);
47 static void sata_enable(struct device *dev) { /* TODO */ }
49 static struct device_operations sata_ops = {
50 .read_resources = pci_dev_read_resources,
51 .set_resources = pci_dev_set_resources,
52 .enable_resources = pci_dev_enable_resources,
53 .init = sata_init,
54 .enable = sata_enable,
55 .ops_pci = &soc_pci_ops,
58 static const unsigned short pci_device_ids[] = {
59 PCI_DID_INTEL_DNV_SATA_AHCI_1,
60 PCI_DID_INTEL_DNV_SATA_AHCI_2,
64 static const struct pci_driver soc_sata __pci_driver = {
65 .ops = &sata_ops,
66 .vendor = PCI_VID_INTEL,
67 .devices = pci_device_ids,