src/soc/intel/jasperlake/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_JASPERLAKE
   4         bool
   5         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   6         select ARCH_X86
   7         select BOOT_DEVICE_SUPPORTS_WRITES
   8         select CACHE_MRC_SETTINGS
   9         select CPU_INTEL_COMMON
  10         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  11         select CPU_SUPPORTS_PM_TIMER_EMULATION
  12         select COS_MAPPED_TO_MSB
  13         select DISPLAY_FSP_VERSION_INFO_2
  14         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  15         select FSP_COMPRESS_FSP_S_LZ4
  16         select FSP_M_XIP
  17         select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
  18         select GENERIC_GPIO_LIB
  19         select HAVE_DPTF_EISA_HID
  20         select HAVE_FSP_GOP
  21         select INTEL_DESCRIPTOR_MODE_CAPABLE
  22         select HAVE_SMI_HANDLER
  23         select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
  24         select IDT_IN_EVERY_STAGE
  25         select INTEL_CAR_NEM_ENHANCED
  26         select INTEL_GMA_ACPI
  27         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  28         select MP_SERVICES_PPI_V1
  29         select MRC_SETTINGS_PROTECT
  30         select PARALLEL_MP_AP_WORK
  31         select PLATFORM_USES_FSP2_2
  32         select PMC_GLOBAL_RESET_ENABLE_LOCK
  33         select SOC_INTEL_COMMON
  34         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  35         select SOC_INTEL_COMMON_BLOCK
  36         select SOC_INTEL_COMMON_BLOCK_ACPI
  37         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  38         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  39         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  40         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  41         select SOC_INTEL_COMMON_BLOCK_CAR
  42         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  43         select SOC_INTEL_COMMON_BLOCK_CNVI
  44         select SOC_INTEL_COMMON_BLOCK_CPU
  45         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  46         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  47         select SOC_INTEL_COMMON_BLOCK_DTT
  48         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  49         select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
  50         select SOC_INTEL_COMMON_BLOCK_HDA
  51         select SOC_INTEL_COMMON_BLOCK_ME_SPEC_13
  52         select SOC_INTEL_COMMON_BLOCK_SA
  53         select SOC_INTEL_COMMON_BLOCK_SCS
  54         select SOC_INTEL_COMMON_BLOCK_SMM
  55         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  56         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  57         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  58         select SOC_INTEL_COMMON_FSP_RESET
  59         select SOC_INTEL_COMMON_PCH_CLIENT
  60         select SOC_INTEL_COMMON_RESET
  61         select SOC_INTEL_CSE_SEND_EOP_LATE
  62         select SOC_INTEL_CSE_SET_EOP
  63         select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
  64         select SSE2
  65         select SUPPORT_CPU_UCODE_IN_CBFS
  66         select TSC_MONOTONIC_TIMER
  67         select UDELAY_TSC
  68         select UDK_202005_BINDING
  69         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  70         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  71         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  72         select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
  73         help
  74           Intel Jasperlake support
  75
  76 if SOC_INTEL_JASPERLAKE
  77
  78 config DCACHE_RAM_BASE
  79         default 0xfef00000
  80
  81 config DCACHE_RAM_SIZE
  82         default 0x80000
  83         help
  84           The size of the cache-as-ram region required during bootblock
  85           and/or romstage.
  86
  87 config DCACHE_BSP_STACK_SIZE
  88         hex
  89         default 0x30400
  90         help
  91           The amount of anticipated stack usage in CAR by bootblock and
  92           other stages. In the case of FSP_USES_CB_STACK default value
  93           will be sum of FSP-M stack requirement(192 KiB) and CB romstage
  94           stack requirement(~1KiB).
  95
  96 config FSP_TEMP_RAM_SIZE
  97         hex
  98         default 0x20000
  99         help
 100           The amount of anticipated heap usage in CAR by FSP.
 101           Refer to Platform FSP integration guide document to know
 102           the exact FSP requirement for Heap setup.
 103
 104 config IFD_CHIPSET
 105         string
 106         default "jsl"
 107
 108 config IED_REGION_SIZE
 109         hex
 110         default 0x400000
 111
 112 config MAX_ROOT_PORTS
 113         int
 114         default 8
 115
 116 config MAX_PCIE_CLOCK_SRC
 117         int
 118         default 6
 119
 120 config SMM_TSEG_SIZE
 121         hex
 122         default 0x800000
 123
 124 config SMM_RESERVED_SIZE
 125         hex
 126         default 0x200000
 127
 128 config PCR_BASE_ADDRESS
 129         hex
 130         default 0xfd000000
 131         help
 132           This option allows you to select MMIO Base Address of sideband bus.
 133
 134 config ECAM_MMCONF_BASE_ADDRESS
 135         default 0xc0000000
 136
 137 config CPU_BCLK_MHZ
 138         int
 139         default 100
 140
 141 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 142         int
 143         default 120
 144
 145 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 146         int
 147         default 133
 148
 149 config CPU_XTAL_HZ
 150         default 38400000
 151
 152 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 153         int
 154         default 3
 155
 156 config SOC_INTEL_I2C_DEV_MAX
 157         int
 158         default 6
 159
 160 config SOC_INTEL_UART_DEV_MAX
 161         int
 162         default 3
 163
 164 config CONSOLE_UART_BASE_ADDRESS
 165         hex
 166         default 0xfe032000
 167         depends on INTEL_LPSS_UART_FOR_CONSOLE
 168
 169 # Clock divider parameters for 115200 baud rate
 170 # Baudrate = (UART source clock * M) /(N *16)
 171 # JSL UART source clock: 100MHz
 172 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 173         hex
 174         default 0x30
 175
 176 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 177         hex
 178         default 0xc35
 179
 180 config VBOOT
 181         select VBOOT_MUST_REQUEST_DISPLAY
 182         select VBOOT_STARTS_IN_BOOTBLOCK
 183         select VBOOT_VBNV_CMOS
 184         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 185
 186 config CBFS_SIZE
 187         default 0x200000
 188
 189 config FSP_HEADER_PATH
 190         default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"
 191
 192 config FSP_FD_PATH
 193         default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
 194
 195 config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT
 196         int "Debug Consent for JSL"
 197         # USB DBC is more common for developers so make this default to 3 if
 198         # SOC_INTEL_DEBUG_CONSENT=y
 199         default 3 if SOC_INTEL_DEBUG_CONSENT
 200         default 0
 201         help
 202           This is to control debug interface on SOC.
 203           Setting non-zero value will allow to use DBC or DCI to debug SOC.
 204           PlatformDebugConsent in FspmUpd.h has the details.
 205
 206           Desired platform debug type are
 207           0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
 208           3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
 209           6:Enable (2-wire DCI OOB), 7:Manual
 210
 211 config PRERAM_CBMEM_CONSOLE_SIZE
 212         hex
 213         default 0x1400
 214
 215 config INTEL_GMA_BCLV_OFFSET
 216         default 0xc8258
 217
 218 config INTEL_GMA_BCLV_WIDTH
 219         default 32
 220
 221 config INTEL_GMA_BCLM_OFFSET
 222         default 0xc8254
 223
 224 config INTEL_GMA_BCLM_WIDTH
 225         default 32
 226 endif