src/soc/intel/jasperlake/Makefile.mk

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2 ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
   3
   4 subdirs-y += romstage
   5 subdirs-y += ../../../cpu/intel/microcode
   6 subdirs-y += ../../../cpu/intel/turbo
   7
   8 # all (bootblock, verstage, romstage, postcar, ramstage)
   9 all-y += gspi.c
  10 all-y += i2c.c
  11 all-y += pmutil.c
  12 all-y += spi.c
  13 all-y += uart.c
  14
  15 bootblock-y += bootblock/bootblock.c
  16 bootblock-y += bootblock/pch.c
  17 bootblock-y += bootblock/report_platform.c
  18 bootblock-y += espi.c
  19 bootblock-y += gpio.c
  20 bootblock-y += p2sb.c
  21
  22 romstage-y += espi.c
  23 romstage-y += gpio.c
  24 romstage-y += meminit.c
  25 romstage-y += pcie_rp.c
  26 romstage-y += reset.c
  27
  28 ramstage-y += acpi.c
  29 ramstage-y += chip.c
  30 ramstage-y += cpu.c
  31 ramstage-y += elog.c
  32 ramstage-y += espi.c
  33 ramstage-y += finalize.c
  34 ramstage-y += fsp_params.c
  35 ramstage-y += gpio.c
  36 ramstage-y += graphics.c
  37 ramstage-y += lockdown.c
  38 ramstage-y += p2sb.c
  39 ramstage-y += pcie_rp.c
  40 ramstage-y += pmc.c
  41 ramstage-y += reset.c
  42 ramstage-y += systemagent.c
  43 ramstage-y += sd.c
  44 ramstage-y += xhci.c
  45
  46 smm-y += gpio.c
  47 smm-y += p2sb.c
  48 smm-y += pmutil.c
  49 smm-y += smihandler.c
  50 smm-y += uart.c
  51 smm-y += elog.c
  52 smm-y += xhci.c
  53
  54 verstage-y += gpio.c
  55
  56 CPPFLAGS_common += -I$(src)/soc/intel/jasperlake
  57 CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include
  58
  59 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9c-00
  60
  61 endif