1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #define R_ICLK_PCR_CAMERA1 0x8000
4 #define B_ICLK_PCR_FREQUENCY 0x1
5 #define B_ICLK_PCR_REQUEST 0x2
7 /* The clock control registers for each IMGCLK are offset by 0xC */
8 #define B_ICLK_PCR_OFFSET 0xC
12 /* IsCLK PCH base register for clock settings */
14 ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1
18 * Return : Offset of register to control the clock in Arg0
21 Method (OFST, 0x1, NotSerialized)
23 Return (ICKB + (Arg0 * B_ICLK_PCR_OFFSET))
27 * Helper function for Read And OR Write
28 * Arg0 : source and destination
32 Method (RAOW, 0x3, Serialized)
34 OperationRegion (ICLK, SystemMemory, OFST(Arg0), 4)
35 Field (ICLK, AnyAcc, NoLock, Preserve)
40 VAL0 = Local0 & Arg1 | Arg2
44 * Clock control Method
45 * Arg0: Clock source select(0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3,
46 * 4: IMGCLKOUT_4, 5: IMGCLKOUT_5)
47 * Arg1: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz)
49 Method (MCON, 0x2, NotSerialized)
51 /* Set Clock Frequency */
52 RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1)
55 RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST)
58 Method (MCOF, 0x1, NotSerialized)
61 RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0)