src/soc/intel/jasperlake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <fsp/api.h>
   6 #include <fsp/util.h>
   7 #include <gpio.h>
   8 #include <intelblocks/acpi.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/itss.h>
  11 #include <intelblocks/pcie_rp.h>
  12 #include <intelblocks/systemagent.h>
  13 #include <intelblocks/xdci.h>
  14 #include <soc/intel/common/vbt.h>
  15 #include <soc/itss.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/pcie.h>
  18 #include <soc/ramstage.h>
  19 #include <soc/soc_chip.h>
  20
  21 #if CONFIG(HAVE_ACPI_TABLES)
  22 const char *soc_acpi_name(const struct device *dev)
  23 {
  24         if (dev->path.type == DEVICE_PATH_DOMAIN)
  25                 return "PCI0";
  26
  27         if (dev->path.type == DEVICE_PATH_USB) {
  28                 switch (dev->path.usb.port_type) {
  29                 case 0:
  30                         /* Root Hub */
  31                         return "RHUB";
  32                 case 2:
  33                         /* USB2 ports */
  34                         switch (dev->path.usb.port_id) {
  35                         case 0: return "HS01";
  36                         case 1: return "HS02";
  37                         case 2: return "HS03";
  38                         case 3: return "HS04";
  39                         case 4: return "HS05";
  40                         case 5: return "HS06";
  41                         case 6: return "HS07";
  42                         case 7: return "HS08";
  43                         case 8: return "HS09";
  44                         case 9: return "HS10";
  45                         }
  46                         break;
  47                 case 3:
  48                         /* USB3 ports */
  49                         switch (dev->path.usb.port_id) {
  50                         case 0: return "SS01";
  51                         case 1: return "SS02";
  52                         case 2: return "SS03";
  53                         case 3: return "SS04";
  54                         case 4: return "SS05";
  55                         case 5: return "SS06";
  56                         }
  57                         break;
  58                 }
  59                 return NULL;
  60         }
  61         if (dev->path.type != DEVICE_PATH_PCI)
  62                 return NULL;
  63
  64         switch (dev->path.pci.devfn) {
  65         case SA_DEVFN_ROOT:     return "MCHC";
  66         case SA_DEVFN_IPU:      return "IPU0";
  67         case PCH_DEVFN_ISH:     return "ISHB";
  68         case SA_DEVFN_GNA:      return "GNA";
  69         case PCH_DEVFN_XHCI:    return "XHCI";
  70         case PCH_DEVFN_I2C0:    return "I2C0";
  71         case PCH_DEVFN_I2C1:    return "I2C1";
  72         case PCH_DEVFN_I2C2:    return "I2C2";
  73         case PCH_DEVFN_I2C3:    return "I2C3";
  74         case PCH_DEVFN_I2C4:    return "I2C4";
  75         case PCH_DEVFN_I2C5:    return "I2C5";
  76         case PCH_DEVFN_SATA:    return "SATA";
  77         case PCH_DEVFN_PCIE1:   return "RP01";
  78         case PCH_DEVFN_PCIE2:   return "RP02";
  79         case PCH_DEVFN_PCIE3:   return "RP03";
  80         case PCH_DEVFN_PCIE4:   return "RP04";
  81         case PCH_DEVFN_PCIE5:   return "RP05";
  82         case PCH_DEVFN_PCIE6:   return "RP06";
  83         case PCH_DEVFN_PCIE7:   return "RP07";
  84         case PCH_DEVFN_PCIE8:   return "RP08";
  85         case PCH_DEVFN_PCIE9:   return "RP09";
  86         case PCH_DEVFN_PCIE10:  return "RP10";
  87         case PCH_DEVFN_PCIE11:  return "RP11";
  88         case PCH_DEVFN_PCIE12:  return "RP12";
  89         case PCH_DEVFN_UART0:   return "UAR0";
  90         case PCH_DEVFN_UART1:   return "UAR1";
  91         case PCH_DEVFN_UART2:   return "UAR2";
  92         case PCH_DEVFN_GSPI0:   return "SPI0";
  93         case PCH_DEVFN_GSPI1:   return "SPI1";
  94         case PCH_DEVFN_GSPI2:   return "SPI2";
  95         case PCH_DEVFN_GSPI3:   return "SPI3";
  96         case PCH_DEVFN_EMMC:    return "EMMC";
  97         case PCH_DEVFN_SDCARD:  return "SDXC";
  98         case PCH_DEVFN_HDA:     return "HDAS";
  99         case PCH_DEVFN_SMBUS:   return "SBUS";
 100         case PCH_DEVFN_GBE:     return "GLAN";
 101         }
 102
 103         return NULL;
 104 }
 105 #endif
 106
 107 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
 108 static void soc_fill_gpio_pm_configuration(void)
 109 {
 110         uint8_t value[TOTAL_GPIO_COMM];
 111         const config_t *config = config_of_soc();
 112
 113         if (config->gpio_override_pm)
 114                 memcpy(value, config->gpio_pm, sizeof(value));
 115         else
 116                 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
 117
 118         gpio_pm_configure(value, TOTAL_GPIO_COMM);
 119 }
 120
 121 void soc_init_pre_device(void *chip_info)
 122 {
 123         /* Perform silicon specific init. */
 124         fsp_silicon_init();
 125
 126          /* Display FIRMWARE_VERSION_INFO_HOB */
 127         fsp_display_fvi_version_hob();
 128
 129         soc_fill_gpio_pm_configuration();
 130
 131         /* swap enabled PCI ports in device tree if needed */
 132         pcie_rp_update_devicetree(pch_rp_groups);
 133 }
 134
 135 static struct device_operations pci_domain_ops = {
 136         .read_resources   = &pci_domain_read_resources,
 137         .set_resources    = &pci_domain_set_resources,
 138         .scan_bus         = &pci_host_bridge_scan_bus,
 139 #if CONFIG(HAVE_ACPI_TABLES)
 140         .acpi_name        = &soc_acpi_name,
 141         .acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 142 #endif
 143 };
 144
 145 static struct device_operations cpu_bus_ops = {
 146         .read_resources   = noop_read_resources,
 147         .set_resources    = noop_set_resources,
 148 #if CONFIG(HAVE_ACPI_TABLES)
 149         .acpi_fill_ssdt   = generate_cpu_entries,
 150 #endif
 151 };
 152
 153 extern struct device_operations pmc_ops;
 154 static void soc_enable(struct device *dev)
 155 {
 156         /* Set the operations if it is a special bus type */
 157         if (dev->path.type == DEVICE_PATH_DOMAIN)
 158                 dev->ops = &pci_domain_ops;
 159         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 160                 dev->ops = &cpu_bus_ops;
 161         else if (dev->path.type == DEVICE_PATH_PCI &&
 162                  dev->path.pci.devfn == PCH_DEVFN_PMC)
 163                 dev->ops = &pmc_ops;
 164         else if (dev->path.type == DEVICE_PATH_GPIO)
 165                 block_gpio_enable(dev);
 166 }
 167
 168 struct chip_operations soc_intel_jasperlake_ops = {
 169         .name = "Intel Jasperlake",
 170         .enable_dev     = &soc_enable,
 171         .init           = &soc_init_pre_device,
 172 };