src/soc/intel/jasperlake/elog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <device/pci_ops.h>
   6 #include <elog.h>
   7 #include <intelblocks/pmclib.h>
   8 #include <intelblocks/xhci.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/pm.h>
  11 #include <types.h>
  12
  13 struct pme_map {
  14         unsigned int devfn;
  15         unsigned int wake_source;
  16 };
  17
  18 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
  19 {
  20         int i;
  21
  22         gpe0_sts &= gpe0_en;
  23
  24         for (i = 0; i <= 31; i++) {
  25                 if (gpe0_sts & (1 << i))
  26                         elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
  27         }
  28 }
  29
  30 static void pch_log_rp_wake_source(void)
  31 {
  32         size_t i;
  33
  34         const struct pme_map pme_map[] = {
  35                 { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 },
  36                 { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 },
  37                 { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 },
  38                 { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 },
  39                 { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 },
  40                 { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 },
  41                 { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 },
  42                 { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 },
  43                 { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 },
  44                 { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 },
  45                 { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 },
  46                 { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
  47         };
  48
  49         for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) {
  50                 if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(pme_map[i].devfn),
  51                                                    PCI_FUNC(pme_map[i].devfn))))
  52                         elog_add_event_wake(pme_map[i].wake_source, 0);
  53         }
  54 }
  55
  56 static void pch_log_pme_internal_wake_source(void)
  57 {
  58         size_t i;
  59         bool dev_found = false;
  60
  61         const struct pme_map ipme_map[] = {
  62                 { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA },
  63                 { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE },
  64                 { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA },
  65                 { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE },
  66                 { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI },
  67                 { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI },
  68         };
  69         const struct xhci_wake_info xhci_wake_info[] = {
  70                 { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI },
  71         };
  72
  73         for (i = 0; i < ARRAY_SIZE(ipme_map); i++) {
  74                 if (pci_dev_is_wake_source(PCI_DEV(0, PCI_SLOT(ipme_map[i].devfn),
  75                                                    PCI_FUNC(ipme_map[i].devfn)))) {
  76                         elog_add_event_wake(ipme_map[i].wake_source, 0);
  77                         dev_found = true;
  78                 }
  79         }
  80
  81         /*
  82          * Check the XHCI controllers' USB2 & USB3 ports for wake events. There
  83          * are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI
  84          * controller's PME_STS_BIT may have already been cleared, so the host
  85          * controller wake wouldn't get logged here; therefore, the host
  86          * controller wake event is logged before its corresponding port wake
  87          * event is logged.
  88          */
  89         dev_found |= xhci_update_wake_event(xhci_wake_info,
  90                                             ARRAY_SIZE(xhci_wake_info));
  91
  92         if (!dev_found)
  93                 elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
  94 }
  95
  96 static void pch_log_wake_source(const struct chipset_power_state *ps)
  97 {
  98         /* Power Button */
  99         if (ps->pm1_sts & PWRBTN_STS)
 100                 elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
 101
 102         /* RTC */
 103         if (ps->pm1_sts & RTC_STS)
 104                 elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
 105
 106         /* PCI Express */
 107         if (ps->pm1_sts & PCIEXPWAK_STS)
 108                 pch_log_rp_wake_source();
 109
 110         /* PME (TODO: determine wake device) */
 111         if (ps->gpe0_sts[GPE_STD] & PME_STS)
 112                 elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
 113
 114         /* Internal PME */
 115         if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
 116                 pch_log_pme_internal_wake_source();
 117
 118         /* SMBUS Wake */
 119         if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
 120                 elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
 121
 122         /* Log GPIO events in set 1-3 */
 123         pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
 124         pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
 125         pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
 126         /* Treat the STD as an extension of GPIO to obtain visibility. */
 127         pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
 128 }
 129
 130 static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 131 {
 132         /* Thermal Trip */
 133         if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
 134                 elog_add_event(ELOG_TYPE_THERM_TRIP);
 135
 136         /* PWR_FLR Power Failure */
 137         if (ps->gen_pmcon_a & PWR_FLR)
 138                 elog_add_event(ELOG_TYPE_POWER_FAIL);
 139
 140         /* SUS Well Power Failure */
 141         if (ps->gen_pmcon_a & SUS_PWR_FLR)
 142                 elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
 143
 144         /* TCO Timeout */
 145         if (ps->prev_sleep_state != ACPI_S3 &&
 146             ps->tco2_sts & TCO2_STS_SECOND_TO)
 147                 elog_add_event(ELOG_TYPE_TCO_RESET);
 148
 149         /* Power Button Override */
 150         if (ps->pm1_sts & PRBTNOR_STS)
 151                 elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
 152
 153         /* RTC reset */
 154         if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
 155                 elog_add_event(ELOG_TYPE_RTC_RESET);
 156
 157         /* Host Reset Status */
 158         if (ps->gen_pmcon_a & HOST_RST_STS)
 159                 elog_add_event(ELOG_TYPE_SYSTEM_RESET);
 160
 161         /* ACPI Wake Event */
 162         if (ps->prev_sleep_state != ACPI_S0)
 163                 elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
 164 }
 165
 166 static void pch_log_state(void *unused)
 167 {
 168         struct chipset_power_state *ps = pmc_get_power_state();
 169
 170         if (!ps) {
 171                 printk(BIOS_ERR, "chipset_power_state not found!\n");
 172                 return;
 173         }
 174
 175         /* Power and Reset */
 176         pch_log_power_and_resets(ps);
 177
 178         /* Wake Sources */
 179         if (ps->prev_sleep_state > ACPI_S0)
 180                 pch_log_wake_source(ps);
 181 }
 182
 183 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
 184
 185 void elog_gsmi_cb_platform_log_wake_source(void)
 186 {
 187         struct chipset_power_state ps;
 188         pmc_fill_pm_reg_info(&ps);
 189         pch_log_wake_source(&ps);
 190 }