src/soc/intel/jasperlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <acpi/acpi_pm.h>
  11 #include <console/console.h>
  12 #include <device/mmio.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <gpio.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/rtc.h>
  18 #include <intelblocks/tco.h>
  19 #include <soc/espi.h>
  20 #include <soc/gpe.h>
  21 #include <soc/iomap.h>
  22 #include <soc/pci_devs.h>
  23 #include <soc/pm.h>
  24 #include <soc/smbus.h>
  25 #include <soc/soc_chip.h>
  26 #include <security/vboot/vbnv.h>
  27
  28 /*
  29  * SMI
  30  */
  31
  32 const char *const *soc_smi_sts_array(size_t *a)
  33 {
  34         static const char *const smi_sts_bits[] = {
  35                 [BIOS_STS_BIT] = "BIOS",
  36                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  37                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  38                 [APM_STS_BIT] = "APM",
  39                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  40                 [PM1_STS_BIT] = "PM1",
  41                 [GPE0_STS_BIT] = "GPE0",
  42                 [GPIO_STS_BIT] = "GPI",
  43                 [MCSMI_STS_BIT] = "MCSMI",
  44                 [DEVMON_STS_BIT] = "DEVMON",
  45                 [TCO_STS_BIT] = "TCO",
  46                 [PERIODIC_STS_BIT] = "PERIODIC",
  47                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  48                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  49                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  50                 [MONITOR_STS_BIT] = "MONITOR",
  51                 [SPI_SMI_STS_BIT] = "SPI",
  52                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  53                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  54         };
  55
  56         *a = ARRAY_SIZE(smi_sts_bits);
  57         return smi_sts_bits;
  58 }
  59
  60 /*
  61  * TCO
  62  */
  63
  64 const char *const *soc_tco_sts_array(size_t *a)
  65 {
  66         static const char *const tco_sts_bits[] = {
  67                 [0] = "NMI2SMI",
  68                 [1] = "SW_TCO",
  69                 [2] = "TCO_INT",
  70                 [3] = "TIMEOUT",
  71                 [7] = "NEWCENTURY",
  72                 [8] = "BIOSWR",
  73                 [9] = "DMISCI",
  74                 [10] = "DMISMI",
  75                 [12] = "DMISERR",
  76                 [13] = "SLVSEL",
  77                 [16] = "INTRD_DET",
  78                 [17] = "SECOND_TO",
  79                 [18] = "BOOT",
  80                 [20] = "SMLINK_SLV"
  81         };
  82
  83         *a = ARRAY_SIZE(tco_sts_bits);
  84         return tco_sts_bits;
  85 }
  86
  87 /*
  88  * GPE0
  89  */
  90
  91 const char *const *soc_std_gpe_sts_array(size_t *a)
  92 {
  93         static const char *const gpe_sts_bits[] = {
  94                 [1] = "HOTPLUG",
  95                 [2] = "SWGPE",
  96                 [6] = "TCO_SCI",
  97                 [7] = "SMB_WAK",
  98                 [9] = "PCI_EXP",
  99                 [10] = "BATLOW",
 100                 [11] = "PME",
 101                 [12] = "ME",
 102                 [13] = "PME_B0",
 103                 [14] = "eSPI",
 104                 [15] = "GPIO Tier-2",
 105                 [16] = "LAN_WAKE",
 106                 [18] = "WADT"
 107         };
 108
 109         *a = ARRAY_SIZE(gpe_sts_bits);
 110         return gpe_sts_bits;
 111 }
 112
 113 void pmc_set_disb(void)
 114 {
 115         /* Set the DISB after DRAM init */
 116         uint8_t disb_val;
 117         /* Only care about bits [23:16] of register GEN_PMCON_A */
 118         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 119
 120         disb_val = read8(addr);
 121         disb_val |= (DISB >> 16);
 122
 123         /* Don't clear bits that are write-1-to-clear */
 124         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 125         write8(addr, disb_val);
 126 }
 127
 128 /*
 129  * PMC controller gets hidden from PCI bus
 130  * during FSP-Silicon init call. Hence PWRMBASE
 131  * can't be accessible using PCI configuration space
 132  * read/write.
 133  */
 134 uint8_t *pmc_mmio_regs(void)
 135 {
 136         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 137 }
 138
 139 uintptr_t soc_read_pmc_base(void)
 140 {
 141         return (uintptr_t)pmc_mmio_regs();
 142 }
 143
 144 uint32_t *soc_pmc_etr_addr(void)
 145 {
 146         return (uint32_t *)(soc_read_pmc_base() + ETR);
 147 }
 148
 149 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 150 {
 151         DEVTREE_CONST struct soc_intel_jasperlake_config *config;
 152
 153         config = config_of_soc();
 154
 155         /* Assign to out variable */
 156         *dw0 = config->pmc_gpe0_dw0;
 157         *dw1 = config->pmc_gpe0_dw1;
 158         *dw2 = config->pmc_gpe0_dw2;
 159 }
 160
 161 static int rtc_failed(uint32_t gen_pmcon_b)
 162 {
 163         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 164 }
 165
 166 static void clear_rtc_failed(void)
 167 {
 168         clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD);
 169 }
 170
 171 static int check_rtc_failed(uint32_t gen_pmcon_b)
 172 {
 173         const int failed = rtc_failed(gen_pmcon_b);
 174         if (failed) {
 175                 clear_rtc_failed();
 176                 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed);
 177         }
 178
 179         return failed;
 180 }
 181
 182 int soc_get_rtc_failed(void)
 183 {
 184         const struct chipset_power_state *ps;
 185
 186         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 187                 return 1;
 188
 189         return check_rtc_failed(ps->gen_pmcon_b);
 190 }
 191
 192 int vbnv_cmos_failed(void)
 193 {
 194         return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 195 }
 196
 197 static inline int deep_s3_enabled(void)
 198 {
 199         uint32_t deep_s3_pol;
 200
 201         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 202         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 203 }
 204
 205 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 206 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 207 {
 208         /*
 209          * Check for any power failure to determine if this a wake from
 210          * S5 because the PCH does not set the WAK_STS bit when waking
 211          * from a true G3 state.
 212          */
 213         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 214                 prev_sleep_state = ACPI_S5;
 215
 216         /*
 217          * If waking from S3 determine if deep S3 is enabled. If not,
 218          * need to check both deep sleep well and normal suspend well.
 219          * Otherwise just check deep sleep well.
 220          */
 221         if (prev_sleep_state == ACPI_S3) {
 222                 /* PWR_FLR represents deep sleep power well loss. */
 223                 uint32_t mask = PWR_FLR;
 224
 225                 /* If deep s3 isn't enabled check the suspend well too. */
 226                 if (!deep_s3_enabled())
 227                         mask |= SUS_PWR_FLR;
 228
 229                 if (ps->gen_pmcon_a & mask)
 230                         prev_sleep_state = ACPI_S5;
 231         }
 232
 233         return prev_sleep_state;
 234 }
 235
 236 void soc_fill_power_state(struct chipset_power_state *ps)
 237 {
 238         uint8_t *pmc;
 239
 240         ps->tco1_sts = tco_read_reg(TCO1_STS);
 241         ps->tco2_sts = tco_read_reg(TCO2_STS);
 242
 243         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 244
 245         pmc = pmc_mmio_regs();
 246         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 247         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 248         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 249         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 250
 251         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 252                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 253
 254         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 255                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 256 }
 257
 258 /* STM Support */
 259 uint16_t get_pmbase(void)
 260 {
 261         return (uint16_t)ACPI_BASE_ADDRESS;
 262 }
 263
 264 /*
 265  * Set which power state system will be after reapplying
 266  * the power (from G3 State)
 267  */
 268 void pmc_soc_set_afterg3_en(const bool on)
 269 {
 270         uint8_t reg8;
 271         uint8_t *const pmcbase = pmc_mmio_regs();
 272
 273         reg8 = read8(pmcbase + GEN_PMCON_A);
 274         if (on)
 275                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 276         else
 277                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 278         write8(pmcbase + GEN_PMCON_A, reg8);
 279 }