src/soc/intel/meteorlake/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <bootstate.h>
   5 #include <console/console.h>
   6 #include <cpu/x86/smm.h>
   7 #include <device/pci.h>
   8 #include <gpio.h>
   9 #include <intelblocks/cse.h>
  10 #include <intelblocks/lpc_lib.h>
  11 #include <intelblocks/pcr.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/systemagent.h>
  14 #include <intelblocks/tco.h>
  15 #include <intelblocks/thermal.h>
  16 #include <spi-generic.h>
  17 #include <intelpch/lockdown.h>
  18 #include <soc/p2sb.h>
  19 #include <soc/pci_devs.h>
  20 #include <soc/pcr_ids.h>
  21 #include <soc/pm.h>
  22 #include <soc/smbus.h>
  23 #include <soc/soc_chip.h>
  24 #include <soc/systemagent.h>
  25
  26 static void pch_handle_sideband(config_t *config)
  27 {
  28 }
  29
  30 static void pch_finalize(void)
  31 {
  32         config_t *config = config_of_soc();
  33
  34         /* TCO Lock down */
  35         tco_lockdown();
  36
  37         /* TODO: Add Thermal Configuration */
  38
  39         pch_handle_sideband(config);
  40
  41         pmc_clear_pmcon_sts();
  42 }
  43
  44 static void tbt_finalize(void)
  45 {
  46         int i;
  47         const struct device *dev;
  48
  49         /* Disable Thunderbolt PCIe root ports bus master */
  50         for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
  51                 dev = pcidev_path_on_root(PCI_DEVFN_TBT(i));
  52                 if (dev)
  53                         pci_dev_disable_bus_master(dev);
  54         }
  55 }
  56
  57 static void sa_finalize(void)
  58 {
  59         if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
  60                 sa_lock_pam();
  61 }
  62
  63 static void heci_finalize(void)
  64 {
  65         heci_set_to_d0i3();
  66         if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
  67                 heci1_disable();
  68 }
  69
  70 static void soc_finalize(void *unused)
  71 {
  72         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  73
  74         pch_finalize();
  75         apm_control(APM_CNT_FINALIZE);
  76         tbt_finalize();
  77         sa_finalize();
  78         if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) &&
  79                          CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
  80                 heci_finalize();
  81
  82         /* Indicate finalize step with post code */
  83         post_code(POSTCODE_OS_BOOT);
  84 }
  85
  86 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
  87 /*
  88  * The purpose of this change is to accommodate more time to push out sending
  89  * CSE EOP messages at post.
  90  */
  91 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, soc_finalize, NULL);