src/soc/intel/meteorlake/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <acpi/acpi_pm.h>
  11 #include <console/console.h>
  12 #include <device/mmio.h>
  13 #include <device/device.h>
  14 #include <device/pci.h>
  15 #include <gpio.h>
  16 #include <intelblocks/pmclib.h>
  17 #include <intelblocks/rtc.h>
  18 #include <intelblocks/tco.h>
  19 #include <security/vboot/vbnv.h>
  20 #include <soc/espi.h>
  21 #include <soc/gpe.h>
  22 #include <soc/iomap.h>
  23 #include <soc/pci_devs.h>
  24 #include <soc/pm.h>
  25 #include <soc/smbus.h>
  26 #include <soc/soc_chip.h>
  27 #include <types.h>
  28
  29 /*
  30  * SMI
  31  */
  32 const char *const *soc_smi_sts_array(size_t *a)
  33 {
  34         static const char *const smi_sts_bits[] = {
  35                 [BIOS_STS_BIT] = "BIOS",
  36                 [LEGACY_USB_STS_BIT] = "LEGACY_USB",
  37                 [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
  38                 [APM_STS_BIT] = "APM",
  39                 [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
  40                 [PM1_STS_BIT] = "PM1",
  41                 [GPE0_STS_BIT] = "GPE0",
  42                 [GPIO_STS_BIT] = "GPI",
  43                 [MCSMI_STS_BIT] = "MCSMI",
  44                 [DEVMON_STS_BIT] = "DEVMON",
  45                 [TCO_STS_BIT] = "TCO",
  46                 [PERIODIC_STS_BIT] = "PERIODIC",
  47                 [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI",
  48                 [SMBUS_SMI_STS_BIT] = "SMBUS_SMI",
  49                 [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI",
  50                 [MONITOR_STS_BIT] = "MONITOR",
  51                 [SPI_SMI_STS_BIT] = "SPI",
  52                 [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK",
  53                 [ESPI_SMI_STS_BIT] = "ESPI_SMI",
  54         };
  55
  56         *a = ARRAY_SIZE(smi_sts_bits);
  57         return smi_sts_bits;
  58 }
  59
  60 /*
  61  * TCO
  62  */
  63 const char *const *soc_tco_sts_array(size_t *a)
  64 {
  65         static const char *const tco_sts_bits[] = {
  66                 [0] = "NMI2SMI",
  67                 [1] = "SW_TCO",
  68                 [2] = "TCO_INT",
  69                 [3] = "TIMEOUT",
  70                 [7] = "NEWCENTURY",
  71                 [8] = "BIOSWR",
  72                 [9] = "DMISCI",
  73                 [10] = "DMISMI",
  74                 [12] = "DMISERR",
  75                 [13] = "SLVSEL",
  76                 [16] = "INTRD_DET",
  77                 [17] = "SECOND_TO",
  78                 [18] = "BOOT",
  79                 [20] = "SMLINK_SLV"
  80         };
  81
  82         *a = ARRAY_SIZE(tco_sts_bits);
  83         return tco_sts_bits;
  84 }
  85
  86 /*
  87  * GPE0
  88  */
  89 const char *const *soc_std_gpe_sts_array(size_t *a)
  90 {
  91         static const char *const gpe_sts_bits[] = {
  92                 [1] = "HOTPLUG",
  93                 [2] = "SWGPE",
  94                 [6] = "TCO_SCI",
  95                 [7] = "SMB_WAK",
  96                 [9] = "PCI_EXP",
  97                 [10] = "BATLOW",
  98                 [11] = "PME",
  99                 [12] = "ME",
 100                 [13] = "PME_B0",
 101                 [14] = "eSPI",
 102                 [15] = "GPIO Tier-2",
 103                 [16] = "LAN_WAKE",
 104                 [18] = "WADT"
 105         };
 106
 107         *a = ARRAY_SIZE(gpe_sts_bits);
 108         return gpe_sts_bits;
 109 }
 110
 111 void pmc_set_disb(void)
 112 {
 113         /* Set the DISB after DRAM init */
 114         uint8_t disb_val;
 115         /* Only care about bits [23:16] of register GEN_PMCON_A */
 116         uint8_t *addr = (uint8_t *)(pmc_mmio_regs() + GEN_PMCON_A + 2);
 117
 118         disb_val = read8(addr);
 119         disb_val |= (DISB >> 16);
 120
 121         /* Don't clear bits that are write-1-to-clear */
 122         disb_val &= ~((MS4V | SUS_PWR_FLR) >> 16);
 123         write8(addr, disb_val);
 124 }
 125
 126 /*
 127  * PMC controller gets hidden from PCI bus
 128  * during FSP-Silicon init call. Hence PWRMBASE
 129  * can't be accessible using PCI configuration space
 130  * read/write.
 131  */
 132 uint8_t *pmc_mmio_regs(void)
 133 {
 134         return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 135 }
 136
 137 uint8_t *ioe_pmc_mmio_regs(void)
 138 {
 139         return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS;
 140 }
 141
 142 uintptr_t soc_read_pmc_base(void)
 143 {
 144         return (uintptr_t)pmc_mmio_regs();
 145 }
 146
 147 uint32_t *soc_pmc_etr_addr(void)
 148 {
 149         return (uint32_t *)(soc_read_pmc_base() + ETR);
 150 }
 151
 152 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 153 {
 154         DEVTREE_CONST struct soc_intel_meteorlake_config *config;
 155
 156         config = config_of_soc();
 157
 158         /* Assign to out variable */
 159         *dw0 = config->pmc_gpe0_dw0;
 160         *dw1 = config->pmc_gpe0_dw1;
 161         *dw2 = config->pmc_gpe0_dw2;
 162 }
 163
 164 static int rtc_failed(uint32_t gen_pmcon_b)
 165 {
 166         return !!(gen_pmcon_b & RTC_BATTERY_DEAD);
 167 }
 168
 169 int soc_get_rtc_failed(void)
 170 {
 171         const struct chipset_power_state *ps;
 172
 173         if (acpi_fetch_pm_state(&ps, PS_CLAIMER_RTC) < 0)
 174                 return 1;
 175
 176         return rtc_failed(ps->gen_pmcon_b);
 177 }
 178
 179 int vbnv_cmos_failed(void)
 180 {
 181         return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
 182 }
 183
 184 static inline int deep_s3_enabled(void)
 185 {
 186         uint32_t deep_s3_pol;
 187
 188         deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL);
 189         return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS));
 190 }
 191
 192 /* Return 0, 3, or 5 to indicate the previous sleep state. */
 193 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
 194 {
 195         /*
 196          * Check for any power failure to determine if this a wake from
 197          * S5 because the PCH does not set the WAK_STS bit when waking
 198          * from a true G3 state.
 199          */
 200         if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
 201                 prev_sleep_state = ACPI_S5;
 202
 203         /*
 204          * If waking from S3 determine if deep S3 is enabled. If not,
 205          * need to check both deep sleep well and normal suspend well.
 206          * Otherwise just check deep sleep well.
 207          */
 208         if (prev_sleep_state == ACPI_S3) {
 209                 /* PWR_FLR represents deep sleep power well loss. */
 210                 uint32_t mask = PWR_FLR;
 211
 212                 /* If deep s3 isn't enabled check the suspend well too. */
 213                 if (!deep_s3_enabled())
 214                         mask |= SUS_PWR_FLR;
 215
 216                 if (ps->gen_pmcon_a & mask)
 217                         prev_sleep_state = ACPI_S5;
 218         }
 219
 220         return prev_sleep_state;
 221 }
 222
 223 void soc_fill_power_state(struct chipset_power_state *ps)
 224 {
 225         uint8_t *pmc;
 226
 227         ps->tco1_sts = tco_read_reg(TCO1_STS);
 228         ps->tco2_sts = tco_read_reg(TCO2_STS);
 229
 230         printk(BIOS_DEBUG, "TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
 231
 232         pmc = pmc_mmio_regs();
 233         ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A);
 234         ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 235         ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 236         ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
 237         ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 238
 239         printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 240                 ps->gen_pmcon_a, ps->gen_pmcon_b);
 241
 242         printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 243                 ps->gblrst_cause[0], ps->gblrst_cause[1]);
 244
 245         printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 246 }
 247
 248 /* STM Support */
 249 uint16_t get_pmbase(void)
 250 {
 251         return (uint16_t)ACPI_BASE_ADDRESS;
 252 }
 253
 254 /*
 255  * Set which power state system will be after reapplying
 256  * the power (from G3 State)
 257  */
 258 void pmc_soc_set_afterg3_en(const bool on)
 259 {
 260         uint8_t reg8;
 261         uint8_t *const pmcbase = pmc_mmio_regs();
 262
 263         reg8 = read8(pmcbase + GEN_PMCON_A);
 264         if (on)
 265                 reg8 &= ~SLEEP_AFTER_POWER_FAIL;
 266         else
 267                 reg8 |= SLEEP_AFTER_POWER_FAIL;
 268         write8(pmcbase + GEN_PMCON_A, reg8);
 269 }