src/soc/intel/tigerlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <device/mmio.h>
   8 #include <arch/smp/mpspec.h>
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci_ops.h>
  12 #include <intelblocks/cpulib.h>
  13 #include <intelblocks/pmclib.h>
  14 #include <intelblocks/acpi.h>
  15 #include <soc/cpu.h>
  16 #include <soc/iomap.h>
  17 #include <soc/nvs.h>
  18 #include <soc/pci_devs.h>
  19 #include <soc/pm.h>
  20 #include <soc/soc_chip.h>
  21 #include <soc/systemagent.h>
  22
  23 /*
  24  * List of supported C-states in this processor.
  25  */
  26 enum {
  27         C_STATE_C0,             /* 0 */
  28         C_STATE_C1,             /* 1 */
  29         C_STATE_C1E,            /* 2 */
  30         C_STATE_C6_SHORT_LAT,   /* 3 */
  31         C_STATE_C6_LONG_LAT,    /* 4 */
  32         C_STATE_C7_SHORT_LAT,   /* 5 */
  33         C_STATE_C7_LONG_LAT,    /* 6 */
  34         C_STATE_C7S_SHORT_LAT,  /* 7 */
  35         C_STATE_C7S_LONG_LAT,   /* 8 */
  36         C_STATE_C8,             /* 9 */
  37         C_STATE_C9,             /* 10 */
  38         C_STATE_C10,            /* 11 */
  39         NUM_C_STATES
  40 };
  41
  42 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  43         [C_STATE_C0] = {},
  44         [C_STATE_C1] = {
  45                 .latency = C1_LATENCY,
  46                 .power = C1_POWER,
  47                 .resource = MWAIT_RES(0, 0),
  48         },
  49         [C_STATE_C1E] = {
  50                 .latency = C1_LATENCY,
  51                 .power = C1_POWER,
  52                 .resource = MWAIT_RES(0, 1),
  53         },
  54         [C_STATE_C6_SHORT_LAT] = {
  55                 .latency = C6_LATENCY,
  56                 .power = C6_POWER,
  57                 .resource = MWAIT_RES(2, 0),
  58         },
  59         [C_STATE_C6_LONG_LAT] = {
  60                 .latency = C6_LATENCY,
  61                 .power = C6_POWER,
  62                 .resource = MWAIT_RES(2, 1),
  63         },
  64         [C_STATE_C7_SHORT_LAT] = {
  65                 .latency = C7_LATENCY,
  66                 .power = C7_POWER,
  67                 .resource = MWAIT_RES(3, 0),
  68         },
  69         [C_STATE_C7_LONG_LAT] = {
  70                 .latency = C7_LATENCY,
  71                 .power = C7_POWER,
  72                 .resource = MWAIT_RES(3, 1),
  73         },
  74         [C_STATE_C7S_SHORT_LAT] = {
  75                 .latency = C7_LATENCY,
  76                 .power = C7_POWER,
  77                 .resource = MWAIT_RES(3, 2),
  78         },
  79         [C_STATE_C7S_LONG_LAT] = {
  80                 .latency = C7_LATENCY,
  81                 .power = C7_POWER,
  82                 .resource = MWAIT_RES(3, 3),
  83         },
  84         [C_STATE_C8] = {
  85                 .latency = C8_LATENCY,
  86                 .power = C8_POWER,
  87                 .resource = MWAIT_RES(4, 0),
  88         },
  89         [C_STATE_C9] = {
  90                 .latency = C9_LATENCY,
  91                 .power = C9_POWER,
  92                 .resource = MWAIT_RES(5, 0),
  93         },
  94         [C_STATE_C10] = {
  95                 .latency = C10_LATENCY,
  96                 .power = C10_POWER,
  97                 .resource = MWAIT_RES(6, 0),
  98         },
  99 };
 100
 101 static int cstate_set_non_s0ix[] = {
 102         C_STATE_C1,
 103         C_STATE_C6_LONG_LAT,
 104         C_STATE_C7S_LONG_LAT
 105 };
 106
 107 static int cstate_set_s0ix[] = {
 108         C_STATE_C1,
 109         C_STATE_C7S_LONG_LAT,
 110         C_STATE_C10
 111 };
 112
 113 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 114 {
 115         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 116                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 117         int *set;
 118         int i;
 119
 120         config_t *config = config_of_soc();
 121
 122         int is_s0ix_enable = config->s0ix_enable;
 123
 124         if (is_s0ix_enable) {
 125                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 126                 set = cstate_set_s0ix;
 127         } else {
 128                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 129                 set = cstate_set_non_s0ix;
 130         }
 131
 132         for (i = 0; i < *entries; i++) {
 133                 map[i] = cstate_map[set[i]];
 134                 map[i].ctype = i + 1;
 135         }
 136         return map;
 137 }
 138
 139 void soc_power_states_generation(int core_id, int cores_per_package)
 140 {
 141         config_t *config = config_of_soc();
 142
 143         if (config->eist_enable)
 144                 /* Generate P-state tables */
 145                 generate_p_state_entries(core_id, cores_per_package);
 146 }
 147
 148 void soc_fill_fadt(acpi_fadt_t *fadt)
 149 {
 150         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 151
 152         config_t *config = config_of_soc();
 153
 154         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 155         fadt->pm_tmr_len = 4;
 156
 157         fill_fadt_extended_pm_io(fadt);
 158
 159         if (config->s0ix_enable)
 160                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 161 }
 162
 163 static struct min_sleep_state min_pci_sleep_states[] = {
 164         { SA_DEVFN_ROOT,        ACPI_DEVICE_SLEEP_D3 },
 165         { SA_DEVFN_IGD,         ACPI_DEVICE_SLEEP_D3 },
 166         { SA_DEVFN_IPU,         ACPI_DEVICE_SLEEP_D3 },
 167         { SA_DEVFN_CPU_PCIE,    ACPI_DEVICE_SLEEP_D3 },
 168         { SA_DEVFN_TBT0,        ACPI_DEVICE_SLEEP_D3 },
 169         { SA_DEVFN_TBT1,        ACPI_DEVICE_SLEEP_D3 },
 170         { SA_DEVFN_TBT2,        ACPI_DEVICE_SLEEP_D3 },
 171         { SA_DEVFN_TBT3,        ACPI_DEVICE_SLEEP_D3 },
 172         { SA_DEVFN_GNA,         ACPI_DEVICE_SLEEP_D3 },
 173         { SA_DEVFN_TCSS_XHCI,   ACPI_DEVICE_SLEEP_D3 },
 174         { SA_DEVFN_TCSS_XDCI,   ACPI_DEVICE_SLEEP_D3 },
 175         { SA_DEVFN_TCSS_DMA0,   ACPI_DEVICE_SLEEP_D3 },
 176         { SA_DEVFN_TCSS_DMA1,   ACPI_DEVICE_SLEEP_D3 },
 177         { SA_DEVFN_VMD,         ACPI_DEVICE_SLEEP_D3 },
 178         { PCH_DEVFN_THC0,       ACPI_DEVICE_SLEEP_D3 },
 179         { PCH_DEVFN_THC1,       ACPI_DEVICE_SLEEP_D3 },
 180         { PCH_DEVFN_XHCI,       ACPI_DEVICE_SLEEP_D3 },
 181         { PCH_DEVFN_USBOTG,     ACPI_DEVICE_SLEEP_D3 },
 182         { PCH_DEVFN_SRAM,       ACPI_DEVICE_SLEEP_D3 },
 183         { PCH_DEVFN_CNVI_WIFI,  ACPI_DEVICE_SLEEP_D3 },
 184         { PCH_DEVFN_I2C0,       ACPI_DEVICE_SLEEP_D3 },
 185         { PCH_DEVFN_I2C1,       ACPI_DEVICE_SLEEP_D3 },
 186         { PCH_DEVFN_I2C2,       ACPI_DEVICE_SLEEP_D3 },
 187         { PCH_DEVFN_I2C3,       ACPI_DEVICE_SLEEP_D3 },
 188         { PCH_DEVFN_CSE,        ACPI_DEVICE_SLEEP_D0 },
 189         { PCH_DEVFN_SATA,       ACPI_DEVICE_SLEEP_D3 },
 190         { PCH_DEVFN_I2C4,       ACPI_DEVICE_SLEEP_D3 },
 191         { PCH_DEVFN_I2C5,       ACPI_DEVICE_SLEEP_D3 },
 192         { PCH_DEVFN_UART2,      ACPI_DEVICE_SLEEP_D3 },
 193         { PCH_DEVFN_PCIE1,      ACPI_DEVICE_SLEEP_D0 },
 194         { PCH_DEVFN_PCIE2,      ACPI_DEVICE_SLEEP_D0 },
 195         { PCH_DEVFN_PCIE3,      ACPI_DEVICE_SLEEP_D0 },
 196         { PCH_DEVFN_PCIE4,      ACPI_DEVICE_SLEEP_D0 },
 197         { PCH_DEVFN_PCIE5,      ACPI_DEVICE_SLEEP_D0 },
 198         { PCH_DEVFN_PCIE6,      ACPI_DEVICE_SLEEP_D0 },
 199         { PCH_DEVFN_PCIE7,      ACPI_DEVICE_SLEEP_D0 },
 200         { PCH_DEVFN_PCIE8,      ACPI_DEVICE_SLEEP_D0 },
 201         { PCH_DEVFN_PCIE9,      ACPI_DEVICE_SLEEP_D0 },
 202         { PCH_DEVFN_PCIE10,     ACPI_DEVICE_SLEEP_D0 },
 203         { PCH_DEVFN_PCIE11,     ACPI_DEVICE_SLEEP_D0 },
 204         { PCH_DEVFN_PCIE12,     ACPI_DEVICE_SLEEP_D0 },
 205         { PCH_DEVFN_UART0,      ACPI_DEVICE_SLEEP_D3 },
 206         { PCH_DEVFN_UART1,      ACPI_DEVICE_SLEEP_D3 },
 207         { PCH_DEVFN_GSPI0,      ACPI_DEVICE_SLEEP_D3 },
 208         { PCH_DEVFN_GSPI1,      ACPI_DEVICE_SLEEP_D3 },
 209         { PCH_DEVFN_ESPI,       ACPI_DEVICE_SLEEP_D0 },
 210         { PCH_DEVFN_PMC,        ACPI_DEVICE_SLEEP_D0 },
 211         { PCH_DEVFN_HDA,        ACPI_DEVICE_SLEEP_D0 },
 212         { PCH_DEVFN_SPI,        ACPI_DEVICE_SLEEP_D3 },
 213         { PCH_DEVFN_GBE,        ACPI_DEVICE_SLEEP_D3 },
 214 };
 215
 216 struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
 217 {
 218         *size = ARRAY_SIZE(min_pci_sleep_states);
 219         return min_pci_sleep_states;
 220 }
 221
 222 uint32_t soc_read_sci_irq_select(void)
 223 {
 224         return read32p(soc_read_pmc_base() + IRQ_REG);
 225 }
 226
 227 static unsigned long soc_fill_dmar(unsigned long current)
 228 {
 229         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 230         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 231
 232         if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
 233                 unsigned long tmp = current;
 234
 235                 current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar);
 236                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 237
 238                 acpi_dmar_drhd_fixup(tmp, current);
 239         }
 240
 241         uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 242         bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 243
 244         if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
 245                 unsigned long tmp = current;
 246
 247                 current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar);
 248                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0);
 249
 250                 acpi_dmar_drhd_fixup(tmp, current);
 251         }
 252
 253         /* TCSS Thunderbolt root ports */
 254         for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
 255                 uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
 256                 bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
 257                 if (tbtbar && tbten) {
 258                         unsigned long tmp = current;
 259
 260                         current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar);
 261                         current += acpi_create_dmar_ds_pci_br(current, 0,
 262                                                               SA_DEV_SLOT_TBT, i);
 263
 264                         acpi_dmar_drhd_fixup(tmp, current);
 265                 }
 266         }
 267
 268         uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 269         bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 270
 271         if (vtvc0bar && vtvc0en) {
 272                 const unsigned long tmp = current;
 273
 274                 current += acpi_create_dmar_drhd_4k(current,
 275                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 276                 current += acpi_create_dmar_ds_ioapic_from_hw(current,
 277                                 IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 278                                 V_P2SB_CFG_IBDF_FUNC);
 279                 current += acpi_create_dmar_ds_msi_hpet(current,
 280                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 281                                 V_P2SB_CFG_HBDF_FUNC);
 282
 283                 acpi_dmar_drhd_fixup(tmp, current);
 284         }
 285
 286         /* Add RMRR entry */
 287         const unsigned long tmp = current;
 288         current += acpi_create_dmar_rmrr(current, 0,
 289                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 290         current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 291         acpi_dmar_rmrr_fixup(tmp, current);
 292
 293         return current;
 294 }
 295
 296 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 297                                    struct acpi_rsdp *rsdp)
 298 {
 299         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 300
 301         /*
 302          * Create DMAR table only if we have VT-d capability and FSP does not override its
 303          * feature.
 304          */
 305         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 306             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 307                 return current;
 308
 309         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 310         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 311         current += dmar->header.length;
 312         current = acpi_align_current(current);
 313         acpi_add_table(rsdp, dmar);
 314
 315         return current;
 316 }
 317
 318 void soc_fill_gnvs(struct global_nvs *gnvs)
 319 {
 320         config_t *config = config_of_soc();
 321
 322         /* Enable DPTF based on mainboard configuration */
 323         gnvs->dpte = config->dptf_enable;
 324
 325         /* Set USB2/USB3 wake enable bitmaps. */
 326         gnvs->u2we = config->usb2_wake_enable_bitmap;
 327         gnvs->u3we = config->usb3_wake_enable_bitmap;
 328 }
 329
 330 int soc_madt_sci_irq_polarity(int sci)
 331 {
 332         return MP_IRQ_POLARITY_HIGH;
 333 }