src/soc/intel/tigerlake/soundwire.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi_soundwire.h>
   4 #include <console/console.h>
   5 #include <device/mmio.h>
   6 #include <device/soundwire.h>
   7 #include <drivers/intel/soundwire/soundwire.h>
   8 #include <intelblocks/pmclib.h>
   9 #include <string.h>
  10
  11 static const struct soundwire_link link_xtal_38_4 = {
  12         .clock_stop_mode0_supported = 1,
  13         .clock_stop_mode1_supported = 1,
  14         .clock_frequencies_supported_count = 1,
  15         .clock_frequencies_supported = { 4800 * KHz },
  16         .default_frame_rate = 48 * KHz,
  17         .default_frame_row_size = 50,
  18         .default_frame_col_size = 4,
  19         .dynamic_frame_shape = 1,
  20         .command_error_threshold = 16,
  21 };
  22
  23 static const struct soundwire_link link_xtal_24 = {
  24         .clock_stop_mode0_supported = 1,
  25         .clock_stop_mode1_supported = 1,
  26         .clock_frequencies_supported_count = 1,
  27         .clock_frequencies_supported = { 6 * MHz },
  28         .default_frame_rate = 48 * KHz,
  29         .default_frame_row_size = 125,
  30         .default_frame_col_size = 2,
  31         .dynamic_frame_shape = 1,
  32         .command_error_threshold = 16,
  33 };
  34
  35 static struct intel_soundwire_controller intel_controller = {
  36         .acpi_address = 0x40000000,
  37         .sdw = {
  38                 .master_list_count = 4
  39         }
  40 };
  41
  42 int soc_fill_soundwire_controller(struct intel_soundwire_controller **controller)
  43 {
  44         const struct soundwire_link *link;
  45         enum pch_pmc_xtal xtal = pmc_get_xtal_freq();
  46         size_t i;
  47
  48         /* Select link config based on XTAL frequency and set IP clock. */
  49         switch (xtal) {
  50         case XTAL_24_MHZ:
  51                 link = &link_xtal_24;
  52                 intel_controller.ip_clock = 24 * MHz;
  53                 break;
  54         case XTAL_38_4_MHZ:
  55                 link = &link_xtal_38_4;
  56                 intel_controller.ip_clock = 38400 * KHz;
  57                 break;
  58         case XTAL_19_2_MHZ:
  59         default:
  60                 printk(BIOS_ERR, "%s: XTAL not supported: 0x%x\n", __func__, xtal);
  61                 return -1;
  62         }
  63
  64         /* Fill link config in controller map based on selected XTAL. */
  65         for (i = 0; i < intel_controller.sdw.master_list_count; i++)
  66                 memcpy(&intel_controller.sdw.master_list[i], link, sizeof(*link));
  67
  68         *controller = &intel_controller;
  69         return 0;
  70 }