src/soc/intel/xeon_sp/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <bootblock_common.h>
   4 #include <console/console.h>
   5 #include <cpu/x86/mtrr.h>
   6 #include <device/pci.h>
   7 #include <fsp/util.h>
   8 #include <FsptUpd.h>
   9 #include <intelblocks/fast_spi.h>
  10 #include <intelblocks/lpc_lib.h>
  11 #include <intelblocks/tco.h>
  12 #include <security/intel/cbnt/cbnt.h>
  13 #include <soc/bootblock.h>
  14 #include <soc/iomap.h>
  15 #include <soc/pci_devs.h>
  16
  17 #if (CONFIG(PLATFORM_USES_FSP2_4))
  18 const FSPT_UPD temp_ram_init_params = {
  19         .FspUpdHeader = {
  20                 .Signature = FSPT_UPD_SIGNATURE,
  21                 .Revision = 2,
  22                 .Reserved = {0},
  23         },
  24         .FsptArchUpd = {
  25                 .Revision = 2,
  26                 .Length = 32,
  27                 .FspDebugHandler = 0,
  28                 .Reserved1 = {0},
  29         },
  30         .FsptCoreUpd = {
  31                 .MicrocodeRegionBase = 0,
  32                 .MicrocodeRegionLength = 0,
  33                 .CodeRegionBase = (UINT64)CACHE_ROM_BASE,
  34                 .CodeRegionLength = (UINT64)CACHE_ROM_SIZE,
  35         },
  36         .FsptConfig = {
  37                 .FsptPort80RouteDisable = 0,
  38                 .ReservedTempRamInitUpd = {0},
  39         },
  40         .UpdTerminator = 0x55AA,
  41 };
  42 #else
  43 const FSPT_UPD temp_ram_init_params = {
  44         .FspUpdHeader = {
  45                 .Signature = FSPT_UPD_SIGNATURE,
  46                 .Revision = 1,
  47                 .Reserved = {0},
  48         },
  49         .FsptCoreUpd = {
  50                 .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
  51                 .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
  52                 .CodeRegionBase = (UINT32)CACHE_ROM_BASE,
  53                 .CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
  54                 .Reserved1 = {0},
  55         },
  56         .FsptConfig = {
  57                 .FsptPort80RouteDisable = 0,
  58                 .ReservedTempRamInitUpd = {0},
  59         },
  60         .UnusedUpdSpace0 = {0},
  61         .UpdTerminator = 0x55AA,
  62 };
  63 #endif //(!CONFIG(PLATFORM_USES_FSP2_4))
  64
  65 static uint64_t assembly_timestamp;
  66 static uint64_t bootblock_timestamp;
  67
  68 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  69 {
  70         /*
  71          * FSP-T does not respect its own API and trashes registers
  72          * coreboot uses to store its initial timestamp.
  73          */
  74         assembly_timestamp = base_timestamp;
  75         bootblock_timestamp = timestamp_get();
  76         fast_spi_cache_bios_region();
  77
  78         bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
  79 }
  80
  81 void bootblock_soc_early_init(void)
  82 {
  83         fast_spi_early_init(SPI_BASE_ADDRESS);
  84         pch_enable_lpc();
  85
  86         /* Set up P2SB BAR. This is needed for PCR to work */
  87         uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
  88         pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
  89         pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
  90 }
  91
  92 void bootblock_soc_init(void)
  93 {
  94         if (assembly_timestamp > bootblock_timestamp)
  95                 printk(BIOS_WARNING, "Invalid initial timestamp detected\n");
  96
  97         if (CONFIG(FSP_CAR))
  98                 report_fspt_output();
  99
 100         if (CONFIG(INTEL_CBNT_LOGGING))
 101                 intel_cbnt_log_registers();
 102
 103         bootblock_pch_init();
 104
 105         /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
 106         tco_configure();
 107
 108         report_platform_info();
 109 }