src/soc/intel/xeon_sp/iio_ioapic.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <intelblocks/acpi.h>
   5 #include <soc/chip_common.h>
   6 #include <soc/util.h>
   7 #include <stdint.h>
   8
   9 static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1];
  10
  11 size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
  12 {
  13         int index = 0;
  14         const IIO_UDS *hob = get_iio_uds();
  15
  16         *ioapic_bases = xeonsp_ioapic_bases;
  17
  18         for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
  19                 if (!soc_cpu_is_enabled(socket))
  20                         continue;
  21                 for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
  22                         const STACK_RES *ri =
  23                                 &hob->PlatformData.IIO_resource[socket].StackRes[stack];
  24                         uint32_t ioapic_base = ri->IoApicBase;
  25                         if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF)
  26                                 continue;
  27                         xeonsp_ioapic_bases[index++] = ioapic_base;
  28                         /*
  29                          * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
  30                          * The IIO IOAPIC is placed at 0x1000 from the reported base.
  31                          */
  32                         if (socket == 0 && stack == 0) {
  33                                 ioapic_base += 0x1000;
  34                                 xeonsp_ioapic_bases[index++] = ioapic_base;
  35                         }
  36                 }
  37         }
  38
  39         return index;
  40 }