src/soc/intel/xeon_sp/pmc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci_ops.h>
   5 #include <intelblocks/pmc.h>
   6 #include <intelblocks/pmclib.h>
   7 #include <intelblocks/rtc.h>
   8 #include <reg_script.h>
   9 #include <soc/pci_devs.h>
  10 #include <soc/pm.h>
  11
  12 #include "chip.h"
  13
  14 /* Fill up PMC resource structure */
  15 int pmc_soc_get_resources(struct pmc_resource_config *cfg)
  16 {
  17         cfg->pwrmbase_offset = PWRMBASE;
  18         cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
  19         cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
  20         cfg->abase_offset = ABASE;
  21         cfg->abase_addr = ACPI_BASE_ADDRESS;
  22         cfg->abase_size = ACPI_BASE_SIZE;
  23
  24         return 0;
  25 }
  26
  27 static const struct reg_script pch_pmc_misc_init_script[] = {
  28         /* Enable SCI and clear SLP requests. */
  29         REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
  30         REG_SCRIPT_END};
  31
  32 static const struct reg_script pmc_write1_to_clear_script[] = {
  33         REG_PCI_OR32(GEN_PMCON_A, 0),
  34         REG_PCI_OR32(GEN_PMCON_B, 0),
  35         REG_PCI_OR32(GEN_PMCON_B, 0),
  36         REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
  37         REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
  38         REG_SCRIPT_END};
  39
  40 void pmc_soc_init(struct device *dev)
  41 {
  42         pmc_set_power_failure_state(true);
  43         pmc_gpe_init();
  44
  45         /* Note that certain bits may be cleared from running script as
  46          * certain bit fields are write 1 to clear. */
  47         reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
  48         pmc_set_acpi_mode();
  49
  50         /* Clear registers that contain write-1-to-clear bits. */
  51         reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
  52 }