src/soc/intel/xeon_sp/pmutil.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * Helper functions for dealing with power management registers
   5  * and the differences between PCH variants.
   6  */
   7
   8 #define __SIMPLE_DEVICE__
   9
  10 #include <device/pci.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/rtc.h>
  13 #include <soc/pci_devs.h>
  14 #include <soc/pm.h>
  15 #include <soc/pmc.h>
  16 #include <types.h>
  17
  18 /*
  19  * SMI
  20  */
  21
  22 const char *const *soc_smi_sts_array(size_t *smi_arr)
  23 {
  24         static const char *const smi_sts_bits[] = {
  25                 [2] = "BIOS",
  26                 [3] = "LEGACY_USB",
  27                 [4] = "SLP_SMI",
  28                 [5] = "APM",
  29                 [6] = "SWSMI_TMR",
  30                 [7] = "BIOS_RLS",
  31                 [8] = "PM1",
  32                 [9] = "GPE0",
  33                 [10] = "GPI",
  34                 [11] = "MCSMI",
  35                 [12] = "DEVMON",
  36                 [13] = "TCO",
  37                 [14] = "PERIODIC",
  38                 [20] = "PCI_EXP_SMI",
  39                 [23] = "IE_SMI",
  40                 [25] = "SCC_SMI",
  41                 [26] = "SPI",
  42                 [27] = "GPIO_UNLOCK",
  43                 [28] = "ESPI_SMI",
  44                 [29] = "SERIAL_I/O",
  45                 [30] = "ME_SMI",
  46                 [31] = "XHCI",
  47         };
  48
  49         *smi_arr = ARRAY_SIZE(smi_sts_bits);
  50         return smi_sts_bits;
  51 }
  52
  53 /*
  54  * TCO
  55  */
  56
  57 const char *const *soc_tco_sts_array(size_t *tco_arr)
  58 {
  59         static const char *const tco_sts_bits[] = {
  60                 [0] = "NMI2SMI",
  61                 [1] = "OS_TCO",
  62                 [2] = "TCO_INT",
  63                 [3] = "TIMEOUT",
  64                 [7] = "NEWCENTURY",
  65                 [8] = "BIOSWR",
  66                 [9] = "CPUSCI",
  67                 [10] = "CPUSMI",
  68                 [12] = "CPUSERR",
  69                 [13] = "SLVSEL",
  70                 [16] = "INTRD_DET",
  71                 [17] = "SECOND_TO",
  72                 [20] = "SMLINK_SLV"
  73         };
  74
  75         *tco_arr = ARRAY_SIZE(tco_sts_bits);
  76         return tco_sts_bits;
  77 }
  78
  79 /*
  80  * GPE0
  81  */
  82
  83 const char *const *soc_std_gpe_sts_array(size_t *gpe_arr)
  84 {
  85         static const char *const gpe_sts_bits[] = {
  86         };
  87
  88         *gpe_arr = ARRAY_SIZE(gpe_sts_bits);
  89         return gpe_sts_bits;
  90 }
  91
  92 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
  93 {
  94         /* No functionality for this yet */
  95 }
  96
  97 /* Return 0, 3, or 5 to indicate the previous sleep state. */
  98 int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state)
  99 {
 100         /*
 101          * Check for any power failure to determine if this a wake from
 102          * S5 because the PCH does not set the WAK_STS bit when waking
 103          * from a true G3 state.
 104          */
 105         if (!(ps->pm1_sts & WAK_STS) &&
 106             (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
 107                 prev_sleep_state = ACPI_S5;
 108
 109         return prev_sleep_state;
 110 }
 111
 112 /* STM Support */
 113 uint16_t get_pmbase(void)
 114 {
 115         return ACPI_BASE_ADDRESS;
 116 }