src/soc/intel/xeon_sp/util.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <commonlib/sort.h>
   5 #include <console/console.h>
   6 #include <delay.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <intelblocks/cfg.h>
  11 #include <intelblocks/cpulib.h>
  12 #include <intelblocks/p2sb.h>
  13 #include <intelpch/lockdown.h>
  14 #include <soc/chip_common.h>
  15 #include <soc/pch_pci_devs.h>
  16 #include <soc/pci_devs.h>
  17 #include <soc/msr.h>
  18 #include <soc/soc_util.h>
  19 #include <soc/util.h>
  20 #include <timer.h>
  21
  22 msr_t read_msr_ppin(void)
  23 {
  24         msr_t ppin = {0};
  25         msr_t msr;
  26
  27         /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
  28         msr = rdmsr(MSR_PLATFORM_INFO);
  29         if ((msr.lo & MSR_PPIN_CAP) == 0) {
  30                 printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
  31                 return ppin;
  32         }
  33
  34         /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
  35         msr = rdmsr(MSR_PPIN_CTL);
  36         if (msr.lo & MSR_PPIN_CTL_LOCK) {
  37                 printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
  38                 return ppin;
  39         }
  40
  41         if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
  42                 /* Set MSR_PPIN_CTL ENABLE to 1 */
  43                 msr.lo |= MSR_PPIN_CTL_ENABLE;
  44                 wrmsr(MSR_PPIN_CTL, msr);
  45         }
  46         ppin = rdmsr(MSR_PPIN);
  47         return ppin;
  48 }
  49
  50 static unsigned int get_threads_per_package(void)
  51 {
  52         unsigned int core_count, thread_count;
  53         cpu_read_topology(&core_count, &thread_count);
  54         return thread_count;
  55 }
  56
  57 int get_platform_thread_count(void)
  58 {
  59         return soc_get_num_cpus() * get_threads_per_package();
  60 }
  61
  62 const IIO_UDS *get_iio_uds(void)
  63 {
  64         size_t hob_size;
  65         static const IIO_UDS *hob;
  66         const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
  67
  68         if (hob)
  69                 return hob;
  70
  71         hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
  72         assert(hob && hob_size != 0);
  73         return hob;
  74 }
  75
  76 /*
  77  * Returns true if the CPU in the specified socket was found
  78  * during QPI init, false otherwise.
  79  */
  80 bool soc_cpu_is_enabled(const size_t idx)
  81 {
  82         const IIO_UDS *hob = get_iio_uds();
  83         assert(idx < CONFIG_MAX_SOCKET);
  84
  85         return hob->PlatformData.IIO_resource[idx].Valid;
  86 }
  87
  88 unsigned int soc_get_num_cpus(void)
  89 {
  90         return get_iio_uds()->SystemStatus.numCpus;
  91 }
  92
  93 union p2sb_bdf soc_get_hpet_bdf(void)
  94 {
  95         if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
  96                 union p2sb_bdf bdf = {
  97                         .bus = HPET_BUS_NUM,
  98                         .dev = HPET_DEV_NUM,
  99                         .fn = HPET0_FUNC_NUM
 100                 };
 101                 return bdf;
 102         }
 103         return p2sb_get_hpet_bdf();
 104 }
 105
 106 union p2sb_bdf soc_get_ioapic_bdf(void)
 107 {
 108         if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) {
 109                 union p2sb_bdf bdf = {
 110                         .bus = PCH_IOAPIC_BUS_NUMBER,
 111                         .dev = PCH_IOAPIC_DEV_NUM,
 112                         .fn = PCH_IOAPIC_FUNC_NUM
 113                 };
 114                 return bdf;
 115         }
 116         return p2sb_get_ioapic_bdf();
 117 }
 118
 119 #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */
 120
 121 void lock_pam0123(void)
 122 {
 123         const uint32_t pam0123_lock = 0x33333331;
 124         struct device *dev;
 125
 126         if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT)
 127                 return;
 128
 129         dev = NULL;
 130         /* Look for SAD_ALL devices on all sockets */
 131         while ((dev = dev_find_device(PCI_VID_INTEL, SAD_ALL_DEVID, dev)))
 132                 pci_write_config32(dev, SAD_ALL_PAM0123_CSR, pam0123_lock);
 133 }
 134
 135 /* return true if command timed out else false */
 136 static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask,
 137                                   uint32_t target)
 138 {
 139         const uint32_t max_delay = 5000; /* 5 seconds max */
 140         const uint32_t step_delay = 50; /* 50 us */
 141         struct stopwatch sw;
 142
 143         stopwatch_init_msecs_expire(&sw, max_delay);
 144         while ((pci_read_config32(pcu1, reg) & mask) != target) {
 145                 udelay(step_delay);
 146                 if (stopwatch_expired(&sw)) {
 147                         printk(BIOS_ERR, "%s timed out for dev: %s, reg: 0x%x, "
 148                                "mask: 0x%x, target: 0x%x\n",
 149                                __func__, dev_path(pcu1), reg, mask, target);
 150                         return true; /* timedout */
 151                 }
 152         }
 153         return false; /* successful */
 154 }
 155
 156 /* return true if command timed out else false */
 157 static bool write_bios_mailbox_cmd(struct device *pcu1, uint32_t command, uint32_t data)
 158 {
 159         /* verify bios is not in busy state */
 160         if (wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
 161                 return true; /* timed out */
 162
 163         /* write data to data register */
 164         printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
 165                PCU_CR1_BIOS_MB_DATA_REG, data);
 166
 167         pci_write_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG, data);
 168
 169         /* write the command */
 170         printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
 171                PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
 172
 173         pci_write_config32(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG,
 174                            command | BIOS_MB_RUN_BUSY_MASK);
 175
 176         /* wait for completion or time out*/
 177         return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG,
 178                                      BIOS_MB_RUN_BUSY_MASK, 0);
 179 }
 180
 181 /* return true if command timed out else false */
 182 static bool set_bios_reset_cpl_for_package(struct device *pcu1,
 183                                            uint32_t rst_cpl_mask,
 184                                            uint32_t pcode_init_mask,
 185                                            uint32_t val)
 186 {
 187         /* update BIOS RESET completion bit */
 188         pci_update_config32(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, ~rst_cpl_mask, val);
 189
 190         /* wait for PCU ack */
 191         return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_RESET_CPL_REG,
 192                                      pcode_init_mask, pcode_init_mask);
 193 }
 194
 195 static void set_bios_init_completion_for_package(uint32_t socket)
 196 {
 197         struct device *pcu0 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR0_DEVID);
 198         struct device *pcu1 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR1_DEVID);
 199         uint32_t data;
 200         bool timedout;
 201
 202         if (!pcu0 || !pcu1)
 203                 die("Failed to locate PCU PCI device\n");
 204
 205         /* read PCU config */
 206         timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0);
 207         if (timedout) {
 208                 /* 2nd try */
 209                 timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0);
 210                 if (timedout)
 211                         die("BIOS PCU Misc Config Read timed out.\n");
 212
 213                 /* Since the 1st try failed, we need to make sure PCU is in stable state */
 214                 data = pci_read_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG);
 215                 printk(BIOS_SPEW, "%s - pci_read_config32 reg: 0x%x, data: 0x%x\n",
 216                         __func__, PCU_CR1_BIOS_MB_DATA_REG, data);
 217                 timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
 218                 if (timedout)
 219                         die("BIOS PCU Misc Config Write timed out.\n");
 220         }
 221
 222         /* update RST_CPL3, PCODE_INIT_DONE3 */
 223         timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL3_MASK,
 224                 PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
 225         if (timedout)
 226                 die("BIOS RESET CPL3 timed out.\n");
 227
 228         /* Set PMAX_LOCK - must be set before RESET CPL4 */
 229         data = pci_read_config32(pcu0, PCU_CR0_PMAX);
 230         data |= PMAX_LOCK;
 231         pci_write_config32(pcu0, PCU_CR0_PMAX, data);
 232
 233         /* update RST_CPL4, PCODE_INIT_DONE4 */
 234         timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL4_MASK,
 235                 PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
 236         if (timedout)
 237                 die("BIOS RESET CPL4 timed out.\n");
 238
 239         /* set CSR_DESIRED_CORES_CFG2 lock bit */
 240         data = pci_read_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG);
 241         data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
 242         printk(BIOS_SPEW, "%s - pci_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
 243                 __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
 244         pci_write_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
 245 }
 246
 247 void set_bios_init_completion(void)
 248 {
 249         uint32_t sbsp_socket_id = 0;
 250
 251         /*
 252          * According to the BIOS Writer's Guide, the SBSP must be the last socket
 253          * to receive the BIOS init completion message. So, we send it to all non-SBSP
 254          * sockets first.
 255          */
 256         for (uint32_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) {
 257                 if (!soc_cpu_is_enabled(socket))
 258                         continue;
 259                 if (socket == sbsp_socket_id)
 260                         continue;
 261                 set_bios_init_completion_for_package(socket);
 262         }
 263
 264         /* And finally, take care of the SBSP */
 265         set_bios_init_completion_for_package(sbsp_socket_id);
 266 }
 267 #endif