src/soc/mediatek/mt8192/pmif_clk.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <commonlib/helpers.h>
   4 #include <delay.h>
   5 #include <device/mmio.h>
   6 #include <soc/infracfg.h>
   7 #include <soc/pll.h>
   8 #include <soc/pll_common.h>
   9 #include <soc/pmif.h>
  10 #include <soc/pmif_clk_common.h>
  11 #include <soc/pmif_sw.h>
  12 #include <soc/pmif_spmi.h>
  13 #include <soc/spm.h>
  14
  15 /* APMIXED, ULPOSC1_CON0 */
  16 DEFINE_BITFIELD(OSC1_CALI, 6, 0)
  17 DEFINE_BITFIELD(OSC1_IBAND, 13, 7)
  18 DEFINE_BITFIELD(OSC1_FBAND, 17, 14)
  19 DEFINE_BITFIELD(OSC1_DIV, 23, 18)
  20 DEFINE_BIT(OSC1_CP_EN, 24)
  21
  22 /* APMIXED, ULPOSC1_CON1 */
  23 DEFINE_BITFIELD(OSC1_32KCALI, 7, 0)
  24 DEFINE_BITFIELD(OSC1_RSV1, 15, 8)
  25 DEFINE_BITFIELD(OSC1_RSV2, 23, 16)
  26 DEFINE_BITFIELD(OSC1_MOD, 25, 24)
  27 DEFINE_BIT(OSC1_DIV2_EN, 26)
  28
  29 /* APMIXED, ULPOSC1_CON2 */
  30 DEFINE_BITFIELD(OSC1_BIAS, 7, 0)
  31
  32 /* SPM, POWERON_CONFIG_EN */
  33 DEFINE_BIT(BCLK_CG_EN, 0)
  34 DEFINE_BITFIELD(PROJECT_CODE, 31, 16)
  35
  36 /* SPM, ULPOSC_CON */
  37 DEFINE_BIT(ULPOSC_EN, 0)
  38 DEFINE_BIT(ULPOSC_CG_EN, 2)
  39
  40 /* INFRA, MODULE_SW_CG */
  41 DEFINE_BIT(PMIC_CG_TMR, 0)
  42 DEFINE_BIT(PMIC_CG_AP, 1)
  43 DEFINE_BIT(PMIC_CG_MD, 2)
  44 DEFINE_BIT(PMIC_CG_CONN, 3)
  45
  46 /* INFRA, INFRA_GLOBALCON_RST2 */
  47 DEFINE_BIT(PMIC_WRAP_SWRST, 0)
  48 DEFINE_BIT(PMICSPMI_SWRST, 14)
  49
  50 /* INFRA, PMICW_CLOCK_CTRL */
  51 DEFINE_BITFIELD(PMIC_SYSCK_26M_SEL, 3, 0)
  52
  53 /* TOPCKGEN, CLK_CFG_8 */
  54 DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SET, 10, 8)
  55 DEFINE_BIT(CLK_PWRAP_ULPOSC_INV, 12)
  56 DEFINE_BIT(PDN_PWRAP_ULPOSC, 15)
  57
  58 /* TOPCKGEN, CLK_CFG_UPDATE1 */
  59 DEFINE_BIT(CLK_CFG_UPDATE1, 2)
  60
  61 static void pmif_ulposc_config(void)
  62 {
  63         /* ULPOSC1_CON0 */
  64         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CP_EN, 0, OSC1_DIV, 0xe,
  65                         OSC1_FBAND, 0x2, OSC1_IBAND, 0x52, OSC1_CALI, 0x40);
  66
  67         /* ULPOSC1_CON1 */
  68         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con1, OSC1_DIV2_EN, 0, OSC1_MOD, 0,
  69                         OSC1_RSV2, 0, OSC1_RSV1, 0x29, OSC1_32KCALI, 0);
  70
  71         /* ULPOSC1_CON2 */
  72         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x40);
  73 }
  74
  75 u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
  76 {
  77         u32 result = 0;
  78
  79         /* set calibration value */
  80         SET32_BITFIELDS(&mtk_apmixed->ulposc1_con0, OSC1_CALI, cali_val);
  81         udelay(50);
  82         result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK);
  83
  84         return result / 1000;
  85 }
  86
  87 static int pmif_init_ulposc(void)
  88 {
  89         /* calibrate ULPOSC1 */
  90         pmif_ulposc_config();
  91
  92         /* enable spm swinf */
  93         if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN))
  94                 SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1,
  95                                 PROJECT_CODE, 0xb16);
  96
  97         /* turn on ulposc */
  98         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1);
  99         udelay(100);
 100         SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1);
 101
 102         return pmif_ulposc_cali(FREQ_260MHZ);
 103 }
 104
 105 int pmif_clk_init(void)
 106 {
 107         if (pmif_init_ulposc())
 108                 return E_NODEV;
 109
 110         /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 111         SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 112                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 113
 114         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_8, PDN_PWRAP_ULPOSC, 0, CLK_PWRAP_ULPOSC_INV,
 115                         0, CLK_PWRAP_ULPOSC_SET, 0);
 116         SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update1, CLK_CFG_UPDATE1, 1);
 117
 118         /* use ULPOSC1 clock */
 119         SET32_BITFIELDS(&mt8192_infracfg->pmicw_clock_ctrl_clr, PMIC_SYSCK_26M_SEL, 0xf);
 120
 121         /* toggle SPI/SPMI sw reset */
 122         SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_set, PMICSPMI_SWRST, 1,
 123                         PMIC_WRAP_SWRST, 1);
 124         SET32_BITFIELDS(&mt8192_infracfg->infra_globalcon_rst2_clr, PMICSPMI_SWRST, 1,
 125                         PMIC_WRAP_SWRST, 1);
 126
 127         /* turn on pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
 128         SET32_BITFIELDS(&mt8192_infracfg->module_sw_cg_0_clr, PMIC_CG_TMR, 1, PMIC_CG_AP, 1,
 129                         PMIC_CG_MD, 1, PMIC_CG_CONN, 1);
 130
 131         return 0;
 132 }